A Rijndael Cryptoprocessor with On-the-fly Key Scheduler

  • Shim, Joon-Hyoung (School of Information Security, Kyungpook National University) ;
  • Bae, Joo-Yeon (School of Electrical Engineering, Kyungpook National University) ;
  • Kang, Yong-Kyu (School of Electrical Engineering, Kyungpook National University) ;
  • Park, Jun-Rim (School of Electrical Engineering, Kyungpook National University)
  • Published : 2002.07.01

Abstract

We implemented a cryptoprocessor with a on-the-fly key scheduler which performs forward key scheduling for encryption and reverse key scheduling for decryption. This scheduler makes the fast generation of the key value and eliminates the memory for software key scheduler. The 128-bit Rijndael processor is implemented based on the proposed architecture using Verilog-HDL and targeted to Xilinx XCV1000E FPGA device. As a result, the 128-bit Rijndael operates at 38.8MHz with on-the-fly key scheduler and consumes 11 cycles for encryption and decryption resulting in a throughput of 451.5Mbps

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