• Proceedings of the Korea Concrete Institute Conference
• /
• 2004.05a
• /
• pp.428-431
• /
• 2004

Smart structural system is defined as structural system with a certain-level of autonomy relying on the embedded functions of sensors, actuators and processors, that can automatically adjust structural characteristics, in response to the change in external disturbance and environments, toward structural safety and serviceability as well as the extension of structural service life. In this study, carbon and glass hybrid fiber materials were investigated fundamentally for the applicability of self diagnosis in smart concrete structural system as embedded functions of sensors.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.5
• /
• pp.229-235
• /
• 2018

As of in the year of 2016, 40 million ARM processors are being shipped everyday and more than 86 billion ARM processors are mounted in mobile communications, consumer electronics, enterprises, and embedded systems. Nationally, we are capable of designing high-end memory semiconductors, but not in processors, resulting in unbalance. Generally, highly expensive software programs are necessary for designing processors which makes it difficult to set up proper environments. However, ModelSim simulator provided by Altera is free and everybody can use it. In this paper, the VHDL language which is widely used in Europe, universities, and research centers around the world for the ASIC design is selected for designing 32-bit ARM processor and simulated by ModelSim. As a result, 37 instructions of ARMv4 has been successfully executed.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.17 no.6
• /
• pp.375-382
• /
• 2022

This paper proposes a multi-core cooperative computing structure considering the heterogeneous features of automotive embedded on-chip software. The automotive embedded software has the heterogeneous execution flow properties for various hardware drives. Software developed with a homogeneous execution flow without considering these properties will incur inefficient overhead due to core latency and load. The proposed method was evaluated on an target board on which a automotive MCU (micro-controller unit) with built-in multi-cores was mounted. We demonstrate an overhead reduction when software including common embedded system tasks, such as ADC sampling, DSP operations, and communication interfaces, are implemented in a heterogeneous execution flow. When we used the proposed method, embedded software was able to take advantage of idle states that occur between heterogeneous tasks to make efficient use of the resources on the board. As a result of the experiments, the power consumption of the board decreased by 42.11% compared to the baseline. Furthermore, the time required to process the same amount of sampling data was reduced by 27.09%. Experimental results validate the efficiency of the proposed multi-core cooperative heterogeneous embedded software execution technique.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.23 no.5
• /
• pp.815-824
• /
• 2013

Traditionally embedded microprocessors is considered as a device for low- and simple-computations because of its limited computing power and constrained resources. However high-end embedded devices have been developed and many applications are getting feasible in the embedded devices. To provide secure and robust service environments, security on embedded devices are in order. Recently many research results on embedded devices have been proposed. In this paper, we explore various cryptography implementation results on representative 8-, 16- and 32-bit embedded processors including AVR, MSP and ARM. This report would be helpful for following researchers who are interested in cryptography implementation techniques on resource constrained devices.

• Journal of the Korea Society of Computer and Information
• /
• v.13 no.6
• /
• pp.33-39
• /
• 2008

Energy efficiency should be considered together with performance when designing embedded processors. This paper proposes a new energy-aware instruction cache design using backward branch information to reduce the energy consumption in an embedded processor, since instruction caches consume a significant fraction of the on-chip energy. Proposed instruction cache is composed of two caches: a large main instruction cache and a small loop instruction cache. Proposed technique enables the selective access between the main instruction cache and the loop instruction cache to reduce the number of accesses to the main instruction cache, leading to good energy efficiency. Analysis results show that the proposed instruction cache reduces the energy consumption by 20% on the average, compared to the traditional instruction cache.

• The KIPS Transactions:PartA
• /
• v.16A no.4
• /
• pp.245-254
• /
• 2009

With the increasing adoption of embedded processors, the need of developing compilers for the embedded processors with timely manner is also growing. Retargeting has been adopted as a viable approach to constructing new compilers by modifying the back-end of an existing compiler. This paper proposes a test suite generation system for testing retargetable C compilers. The proposed system generates the test suite using the grammar coverage concept. Generally, the size of the test suite satisfying the grammar coverage of the source language is very large. Hence, the proposed system also provides the facility to reduce the size of the test suite. According to the experimental result, the reduced test suite can detect 75% of the compiler faults detected by the original test suite though the size of the reduced test suite is only 10% of that of the original test suite in average. This result indicates that the reduction technique proposed in this paper can be effectively used in the prior phase of the development procedure of the embedded compilers.

• 제어로봇시스템학회:학술대회논문집
• /
• 2004.08a
• /
• pp.1675-1678
• /
• 2004

In this paper, web based monitoring systems are implemented for multi-axis force control systems of an intelligence robot. A brief review about the principle of multi-axis force sensors and a method that can reduce the effect of noise signal to sensor performance is presented. A web based monitoring system is implemented by porting Linux at embedded systems which include Xscale processors. A device driver is developed to receive data from multi-axis force sensors in Linux operation systems. To control this device driver, a socket program for web browser is also developed. The experiments are performed to investigate the effectiveness of proposed methods. The experimental results show that the values of force sensors can be monitored by remote PCs.

• Journal of KIISE:Computer Systems and Theory
• /
• v.35 no.7
• /
• pp.305-317
• /
• 2008

As a mobile computing environment is rapidly changing, increasing user demand for multimedia-over-wireless capabilities on embedded processors places constraints on performance, power, and sire. In this regard, this paper proposes color media instructions (CMI) for single instruction, multiple data (SIMD) parallel processors to meet the computational requirements and cost goals. While existing multimedia extensions store and process 48-bit pixels in a 32-bit register, CMI, which considers that color components are perceptually less significant, supports parallel operations on two-packed compressed 16-bit YCbCr (6 bit Y and 5 bits Cb, Cr) data in a 32-bit datapath processor. This provides greater concurrency and efficiency for YCbCr data processing. Moreover, the ability to reduce data format size reduces system cost. The reduction in data bandwidth also simplifies system design. Experimental results on a representative SIMD parallel processor architecture show that CMI achieves an average speedup of 6.3x over the baseline SIMD parallel processor performance. This is in contrast to MMX (a representative Intel's multimedia extensions), which achieves an average speedup of only 3.7x over the same baseline SIMD architecture. CMI also outperforms MMX in both area efficiency (a 52% increase versus a 13% increase) and energy efficiency (a 50% increase versus an 11% increase). CMI improves the performance and efficiency with a mere 3% increase in the system area and a 5% increase in the system power, while MMX requires a 14% increase in the system area and a 16% increase in the system power.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.10 no.1
• /
• pp.148-155
• /
• 2006

Portable embedded systems which mainly handle multimedia applications involve the problem that frequent accesses to fetch data from memory make running time increased. To cope with the problem, embedded processors have adopted data prefetching schemes. From a power point of view, which is a main performance indicator of embedded systems, this paper analyzed to investigate how data prefetching schemes influence on system's performance. To solve the problem, we proposed a power-consumption analysis model of a memory system with data prefetching scheme and measured the power dissipated during running application programs. As a result data prefetching schemes have application program's running time reduced but have system's power increased. Also we proposed a performance analysis model considering execution time and power consumption for embedded system with data prefetching schemes.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.13 no.1
• /
• pp.163-169
• /
• 2013

Recently, the importance of embedded system is growing rapidly. In-order to satisfy the real-time constraints of the system, high performance embedded processor is required. Therefore, as in general purpose computer systems, embedded processor should be designed as multicore architecture as well. Using MiBench benchmarks as input, the trace-driven simulation has been performed and analyzed for the 2-core to 16-core embedded processor architectures with different types of cores from simple RISC to in-order and out-of-order superscalar processors, extensively. As a result, the achievable performance is as high as 23 times over the single core embedded RISC processor.