• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.150-152
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• 2004

The number of layers in rigid PCB(printed circuit board) is restricted, so the number of components can be embedded in module is restricted also. But using flexible multilayer PCB, the layers over than 7 can be evaluated. In this study, to verify the possibility of application of flexible multilayer PCB to RF modules, multilayered embedded capacitor is fabricated and analyzed. The characteristics of embedded capacitor is analyzed and compared to that of MLCC and LTCC capacitor. Embedded capacitor has better electrical features than MLCC and compatible one to LTCC capacitor.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.02a
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• pp.1-14
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• 2006

[ $\blacklozenge$ ] PCB에 있어서 Embedded passive 는chip을 직접 내장하는 방법과 특별한 특성을 갖는 재료 및 공법을 사용하여 chip 응 대치하는 방법이 있다. $\blacklozenge$ Embedded passive PCB가 적용될 수 있는 유력한 적용 분야는 소형화가가 요구되는 분야와 고속 특성이 요구되는 분야를 들 수 있고, 따라서, Module, SOP/SIP, Package substrate 등이 우선적으로 적용될 수 있는 분야다. $\blacklozenge$ Embedded capacitor를 적용한 경우, 일반적인 chip capacitor를 적용한 경우보다 더 좋은 전기적인 특성(SRF, Q)을 얻을 수 있으며, solder joint 등의 영향을 포함하면 더욱 좋은 특성이 얻어질 수 있다. $\blacklozenge$ Embedded passive 의 상용화를 위해서, 공차를 관리하는 방법의 개발과 공차에 대한 합리적인 규격을 설정하는 것이 우선 과제이다. $\blacklozenge$ Embedded resistor 의 경우, Laser trim을 적용하여 ${\pm}\;5\%$ 또는 그 이하의 공차를 실현할 수 있고, $30\;K\Omega/sq$. 의 고저항의 적용까지 가능하다. $\blacklozenge$ 고속 신호에서의 noise 감소, module, SIP/SOP 의 소형화를 실현하는데 Embedded passive(혹은 active)PCB 가 기여 할 수 있을 것이고, 이를 위하여 Set 업체, PCB 업체, 재료 업체간의 지속적인 협조가 필요할 것이다.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.4
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• pp.1-6
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• 2005

Recently embedded passive technology which fabricate passive elements such as resistors and capacitors at the inner layer of PCB(Printed Circuit Board) is used to make high performance IT products. However, embedded capacitor has limit in full range circuit applications because of the low capacitance density. In this paper, a new embedded capacitor which has wrinkled electrodes and dielectric layer was proposed to overcome the limits. FEM(Finite Elements Method) technique was used to evaluate capacitance density of the wrinkled type embedded capacitor. Capacitance density of the wrinkled type embedded capacitor is larger than that of conventional planar type embedded capacitor by about 25.6%$\sim$39.6%. In case of thin film type embedded capacitor, proposed wrinkled structure has more enhanced effect on the capacitance density.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2006.02a
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• pp.33-51
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• 2006

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.72-77
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• 2008

This paper investgated on fabrication process and tolerance of resistance body with a uniform thickness formed by the process of cavity type on organic substrate for application of embedded resistor. To improve the tolerance of resistance value according to a position of PCB cause by conventional screen printing, we introduced the process of cavity type from organic substrate. A resistor with a desired shape and volume was precisely formed by the process of cavity using a resistor paste and screen printing. This method can increase PCB's productivity by shortening its production time because process conditions of a screen prining device can be set quickly without any affection on its position accuracy.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1301-1302
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• 2006

In this paper, embedded spiral inductors are investigated into the PCB substrate for low cost RF SOP applications. The spiral inductors designed with geometrical variations were simulated, fabricated, measured, and characterized by using 3D EM simulator, 8 layered PCB standard process and HP 8510B network analyzer (or verifying their applicability. The fabricated embedded spiral inductor has inductance of 9.4 nH at 800MHz, maximum quality factor of 64.8 at 1.09GHz and self resonant frequency of 3.93GHz, respectively. As the measured inductances and quality factors are well matched with simulated ones. PCB embedded spiral inductors are promising for advanced electronic systems with various functionality, low cost, small size and volume.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.270-270
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• 2007

전자 산업의 발달로 인해 전자기기에 소형화, 경량화 및 다기능화가 요구되면서 민쇄회로기판(PCB)에도 고밀도화, 고집적회가 필요하게 되었다. 이에 따라 embedded passive 기술을 이용하여 기판 내부에 가능한 많은 수동소자들을 실장시키려는 노력이 진행되어지고 있다. 가장 수요가 많은 capacitor의 경우 부피와 전기적 특성 측면에서 내장 효과가 가장 큰 passive 소자에 해당한다. 본 연구에서는 내장형 capacitor의 유전재료로서 중요한 $BaTiO_3$ powder를 filler로 사용하여 epoxy/BT 복합체에서 filler의 분율에 따른 유전상수률 측정하고, filler의 열처리에 따른 유전상수의 변화를 관찰하였다. 그러고 이들 복합체의 mixing rule과 미세구조 관찰을 통하여 기판용 RCC 소재로서의 적용성을 평가하고자 하였다.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.77-82
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• 2012

In this paper, the research of IC embedded PCB process is carried out. For embedding chips into PCB, solder-balls on chips were etched out and ABF(Ajinomoto Build-ip Film), prepreg and Cu foil was laminated on that to fabricate 6 layer build-up board. The chip of which solder ball was removed was successfully interconnected with PCB by laser drilling and Cu plating. However, de-lamination phenomenon occurred between chip surface and ABF during reflow and thermal shock. To solve this problem, de-smear and plasma treatment was applied to PI(polyimide) passivation layer on chip surface to improve the surface roughness. The properties of chip surface(PI) was investigated in terms of AFM(Atomic Force Micrometer), SEM and XPS (X-ray Photoelectron Spectroscopy). As results, nano-size anchor was evenly formed on PI surface when plasma treatment was combined with de-smear(NaOH+KMnO4) process and it improved thermal shock reliability ($260^{\circ}C$-10sec solder floating).

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.67-73
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• 2020

In this paper, we used FEM technique to perform warpage and von Mises stress analysis on PCB according to the cavity structures of embedded PCB for FCCSP and the types of prepreg material. One-half substrate model and static analysis are applied to the FEM. According to the analysis results of the warpage, as the gap between the cavity and the chip increased, warpage increased and warpage increased when prepreg material with higher modularity and thermal expansion coefficient was applied. The analysis results of the von Mises stress show that the effect of the gap between the cavity and the chip varies depending on prepreg material. In other words, when material whose coefficient of thermal expansion is significantly higher than that of core material, the stress increased as the gap between the cavity and the chip increased. When the prepreg with the coefficient of thermal expansion lower than the core material is applied, the result of stress is opposite. These results indicate that from a reliability perspective, there is a correlation between the structure of the cavity where embedded chips are loaded and prepreg material.

• Proceedings of the Korean Society of Computer Information Conference
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• 2020.07a
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• pp.327-328
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• 2020

본 논문에서는 저전력 저비용 임베디드 환경에서 PCB 검사 기법을 제안한다. 특히, IC 미삽에 대한 검출 알고리즘을 제안하고 실험한다. 고사양의 컴퓨팅 시스템에서는 CNN과 같은 딥러닝 뉴럴 네트워크를 사용하여 특별한 알고리즘을 고려하지 않아도 대규모의 데이터를 입력함으로써 모델을 완성하고 이를 통해 PCB 검사를 수행할 수 있다. 그러나 데이터의 양이 충분하지 않거나 충분한 전력과 비용을 투입하지 못하는 임베디드 환경에서는 각 부품에 따른 컴퓨터 비전 알고리즘이 필요하다. IC의 경우 타부품에 비하여 형태가 직사각으로 정형화 되있으며 색상도 균일한 특징을 가지고 있기에 미삽에 대한 검출이 가능하다. 베어보드(Bare Board)의 색상과 IC 부품의 색상이 확연히 다를 경우에는 RGB 픽셀을 카운트 하는 히스토그램 카운팅 알고리즘만으로 검출이 가능하다. 베어보드의 색삭과 IC의 색상이 유사할 경우에는 베어보드의 핀 혹은 홀의 형태를 감지하여 검출이 가능하다. 본 논문에서는 베어보드의 색상와 IC의 색상이 같을 경우에 다를 경우를 나누어 미삽 검사를 수행하고 그 정확도를 확인한다.