• Proceedings of the Korea Contents Association Conference
• /
• 2009.05a
• /
• pp.515-520
• /
• 2009

This paper presents the software design of RFID Educational system based on using 900MHz air interface between the reader and the tag. Software of the reader and active tag is developed on embedded environment and the software of PC controlling the reader is on window OS. ATmega128 processor is used for H/W of the reader and active tag, and C language is used for their developing. Programming on window OS used MFC. Main functions of this system are to control tag containing EPC global Data by PC through the reader, to obtain information of tag through the internet and to read/write data on tag memory. Software design of 900MHz RFID educational system is done on the basis of these functions.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.9B
• /
• pp.1082-1091
• /
• 2011

Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.

• Proceedings of the KSRS Conference
• /
• v.1
• /
• pp.417-420
• /
• 2006

In these days, mobile application dealing with information contents on mobile or handheld devices such as mobile communicator, PDA or WAP device face the most important industrial needs. The motivation of this study is the design and implementation of mobile application using high resolution satellite imagery, large-sized image data set. Although major advantages of mobile devices are portability and mobility to users, limited system resources such as small-sized memory, slow CPU, low power and small screen size are the main obstacles to developers who should handle a large volume of geo-based 3D model. Related to this, the previous works have been concentrated on GIS-based location awareness services on mobile; however, the mobile 3D terrain model, which aims at this study, with the source data of DEM (Digital Elevation Model) and high resolution satellite imagery is not considered yet, in the other mobile systems. The main functions of 3D graphic processing or pixel pipeline in this prototype are implemented with OpenGL|ES (Embedded System) standard API (Application Programming Interface) released by Khronos group. In the developing stage, experiments to investigate optimal operation environment and good performance are carried out: TIN-based vertex generation with regular elevation data, image tiling, and image-vertex texturing, text processing of Unicode type and ASCII type.

• Journal of IKEEE
• /
• v.12 no.2
• /
• pp.118-123
• /
• 2008

The Khronos group releases OpenGL ES 2.0 API specification bringing streamlined shader programming to graphics processor of embedded system. For this reason, the mobile devices have need of graphics processor for supporting a OpenGL ES 2.0 API. We need to extend instruction`s length to support OpenGLES 2.0 API, so it needs more memory size. In this paper, we propose a new instruction format that offers availability for use the instructions. This proposed instruction adopt a variable length method and unit instruction architecture. This proposed instruction architecture that support to OpenGLES 2.0 API has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.5
• /
• pp.229-235
• /
• 2018

As of in the year of 2016, 40 million ARM processors are being shipped everyday and more than 86 billion ARM processors are mounted in mobile communications, consumer electronics, enterprises, and embedded systems. Nationally, we are capable of designing high-end memory semiconductors, but not in processors, resulting in unbalance. Generally, highly expensive software programs are necessary for designing processors which makes it difficult to set up proper environments. However, ModelSim simulator provided by Altera is free and everybody can use it. In this paper, the VHDL language which is widely used in Europe, universities, and research centers around the world for the ASIC design is selected for designing 32-bit ARM processor and simulated by ModelSim. As a result, 37 instructions of ARMv4 has been successfully executed.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.5
• /
• pp.1229-1239
• /
• 1996

The increase of additional information broadcasting of TV demands a graphic overlay processor. This paper is about the design, implementation and testing of a graphic overlay processor called by KBPS decoder ASSP (Applicatio n Specific Standard Product) which is compliance with Korea Broadcast Programming System. KBPS decoder ASSP consists of embedded 8 bit microprocessor Z80, graphic overlay controller, KBPS schedule decoder, memory controller, priority interrupt controller, MIDI controller, infrared raccoon receiver, async scrial communication controller, timer, bus controller, universal parallel input-output port and serial-parallel interface. The 0.8 micron CMOS Sea of Gate is used to implement the ASSP in amount of about 31,500 gates, and it is running at 14.318MHz.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.12
• /
• pp.80-86
• /
• 2003

Elliptic curve cryptosystem(ECC) offers the highest security per bit among the known publick key system. The benefit of smaller key size makes ECC particularly attractive for embedded applications since its implementation requires less memory and processing power. In this paper, we propose a new multiplier structure with configurable output sizes and operation cycles. The number of output bits can be freely chosen in the new architecture with the performance-area trade-off depending on the application. Using the architecture, a 193-bit normal basis multiplier and inversion unit are designed in GF(2$^{m}$ ). It is implemented using HDL and 0.35${\mu}{\textrm}{m}$ CMOS technology and the operation is verified by simulation.

• Annual Conference of KIPS
• /
• 2001.04b
• /
• pp.929-932
• /
• 2001

인터넷 정보 가전(IIA; Internet Information Appliance)내에 내장형 DBMS 의 개발은 다양한 이종 네트워크의 통신을 지원하기 위한 미들웨어(Middleware, i.e. OSGi)의 지원이라는 문제를 해결해야만 하기 때문에, 이들 미들웨어와의 인터페이스라는 문제가 기존의 데이터베이스 엔진을 개발하는 문제와 가장 큰 차이점이라 할 수 있다. 이외에는 일반적인 메모리 상주 데이터베이스 엔진 (nain memory DBMS)을 개발하는 것과는 별다른 큰 차이점이 아직까지는 연구되지 않고 있다. 하지만, 가정이라는 지역적인 특성을 고려한 데이터 서비스를 먼저 염두에 두어야 하며, 이에 따라 다양한 응용 소프트웨어를 쉽게 개발할 수 있는 방향으로 제작이 되어야 한다는 점을 늘 고려해야 한다. 본 논문에서는 이와 같은 인터넷 정보가전용 내장형 DBMS 개발 사업에 관하여 현재까지 본 과제에서 논의되고 있는 요구사항을 분석한 결과를 정리하고, 이에 관한 토론을 하고자 한다.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.8 no.12
• /
• pp.4643-4660
• /
• 2014

Integrity authentication of biometric data in Wireless Body Area Network (WBAN) is a critical issue because the sensitive data transmitted over broadcast wireless channels could be attacked easily. However, traditional cryptograph-based integrity authentication schemes are not suitable for WBAN as they consume much computational resource on the sensor nodes with limited memory, computational capability and power. To address this problem, a novel lightweight integrity authentication scheme based on reversible watermark is proposed for WBAN and implemented on a TinyOS-based WBAN test bed in this paper. In the proposed scheme, the data is divided into groups with a fixed size to improve grouping efficiency; the histogram shifting technique is adopted to avoid possible underflow or overflow; local maps are generated to restore the shifted data; and the watermarks are generated and embedded in a chaining way for integrity authentication. Our analytic and experimental results demonstrate that the integrity of biometric data can be reliably authenticated with low cost, and the data can be entirely recovered for healthcare applications by using our proposed scheme.

• Proceedings of the KOR-BRONCHOESO Conference
• /
• 2003.09a
• /
• pp.107-107
• /
• 2003

Purpose; Tracheal transplantation is necessary in patients with extensive tracheal stenosis, congenital lesions and many oncologic conditions but bears many critical problems compared with other organ transplantations. The purpose of this study was to make an intestine-cartilage composite graft for potential application for tracheal reconstruction by free intestinal graft. Methods; Hyaline cartilage was harvested from trachea of 2 weeks old New Zealand White Rabbits. Chondrocytes were isolated and cultured for 8 weeks. Cultured chodrocytes were seeded in the PLGA scaffolds and mixed in pluronic gel. Chondrocyte bearing scaffolds and gel mixture were embedded in submucosal area of stomach and colon of 3kg weighted New Zealand White Rabbits under general anesthesia. 10 weeks after implantation, bowels were harvested for evaluation. Results; We could identify implantation site by gross examination and palpation. Developed cartilage made a good frame for shape memory Microscopic examinations include special stain showed absorption of scaffold and cartilage formation even though not fully matured Conclusion; Intestine-cartilage composite graft could be applicable to future tracheal substitute and needs further Investigations.