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http://dx.doi.org/10.7840/KICS.2011.36B.9.1082

Power-Minimizing DVFS Algorithm for a Video Decoder with Buffer Constraints  

Jeong, Seung-Ho (서울과학기술대학교 제어계측공학과 임베디드 네트워크 연구실)
Ahn, Hee-June (서울과학기술대학교 제어계측공학과 임베디드 네트워크 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.36, no.9B, 2011 , pp. 1082-1091 More about this Journal
Abstract
Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.
Keywords
video decoder; DVFS; optimal theory; majorization; embedded system;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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