• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.67-74
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• 2004

AES is frequently used as a symmetric cryptography algorithm for the Internet. Wireless embedded systems increasingly use more conventional wired network protocols. Hence, it is important to have low-cost implementations of AES for thor The basic architecture of AES unrolls oかy one full cipher round which uses 20 S-boxes together with the key scheduler and the algorithm repeatedly executes it. To reduce the implementation cost further, the folded architecture which uses only eight S-box units was studied in the recent years. In this paper, we will study a low-cost AES implementation for wireless communication technology based on the folded architecture. We first improve the folded architecture to avoid the sixteen bytes of additional state memory. Then, we implemented a single byte architecture where only one S-box unit is used for data encryption and key scheduling. It takes 352 clocks to finish a complete encryption. We found that the maximum clock frequency of its FPGA implementation reaches about 40 MHz. It can achieve about 13 Mbps which is enough for 3G wireless communication technology.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.147-153
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• 2016

Recently, IETF (Internet Engineering Task) working group has adopted CoAP (Constrained Application Protocol) as a standard IoT proctocol. CoAP is a specialized web transfer protocol for use with constrained nodes and constrained environment such as small memory and low power networks. In this paper, we design and implement a registration service with CoAP protocol based on RD(Resource Directory) to connect IoT nodes in mobile Internet environments. The resource directory between the mobile terminal and IoT nodes provides to discover the IoT nodes and get the context data. The mobile terminal has as the CoAP client and embedded IoT nodes includes as the CoAP server so that it can conveniently manage the constrained IoT nodes to get the context data and control devices in a mobile environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.1B
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• pp.19-25
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• 2006

It's for USB to be used more frequently than another I/O devices. The Universal Serial Bus is the most successful interface in PC history. It's already the do facto interconnect for PCs, and has proliferated into consumer electronics(CE) and mobile devices as well. USB has built on many killer applications, many CE devices, many interfaces. The tangle of wires among the number of devices in your home demands wireless technology. If our devices is unwired, it solves the tangle of wires. In this paper we want to use Legacy USB functionalities, portabilities, multimedia capabilities with wireless interconnection. This paper is related to a study of USB implementation without wires. This paper is related to make the hub function of USB cordless, so it will connect host with devices without wires. In case making USB wireless, it must support the above functionalities. Moreover, It needs the data structure and the resources for host functionalities, e.g. ETD(Endpoint Transfer Descriptor), data memory. This will benefit a convenient use of USB.

• Journal of Internet Computing and Services
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• v.9 no.6
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• pp.117-125
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• 2008

With increase of concern about the Ubiquitous application, the necessity of the computer system which is miniaturized is becoming larger. The ARM processor is showing a high share from embedded system market. In this paper, ideal method for RTD-1000 controller construction and development is described using ARM microcontroller. Existing RTD-1000 measures distance of disconnection or defect of sensing casket by measuring receiving reflected wave which was sent via copper wire inside the leaking sensing rod. Using this RTD-1000, leakage and breakage of water and oil pipe can be sensed and it reports damage results to the networks. But, existing RTD-1000 wastes hardware resources much and costs a great deal to installation. Also, it needs a cooling device because the heating problem, and has some problem of the secondary memory unit such as the hard disk. So, long tenn maintenance has some problems in the outside install place. In this paper, for the resolving the problem of RTD-1000, RTD-1000A embedded system based on ARM is proposed and simulated.

• Anxiety and mood
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• v.16 no.1
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• pp.32-40
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• 2020

Objective : The purpose of this study was to investigate the cognitive performance of major depressive disorder (MDD) in military service/conscription personnel who visited the psychiatric clinic for a medical certificate to consider the situation from the perspective of Korea's unique compulsory military system. We used the Korean Wechsler Adult Intelligence Scale-IV (K-WAIS-IV) as the test for verifying the suitable level of cognitive functioning for military service and as the embedded measure with reflecting suboptimal effort. Methods : The study was conducted on 56 (28 males, age 19-34) in/out-patients admitted to the psychiatry department and diagnosed with MDD (DSM-IV). All participants completed a structured clinical interview (MINI-Plus), as well as self-report questionnaires related to demographics and severity of clinical symptoms. K-WAIS-IV was administered to each subject to assess cognitive characteristics. Results : Military group showed significantly lower processing speed index (PSI) score including subtests of symbol search (SS) and coding (CD) score, compared to the control group. There was no other significant differences in the Full Scale IQ (FSIQ), Verbal Comprehension Index (VCI), Perceptual Reasoning Index (PRI), Working Memory Index (WMI) scores including sub-tests comprised of the above indices, and Reliable Digit Span (RDS), Enhanced-RDS-Revised (E-RDS-R) between the study and control groups. Conclusion : This study was the first effort to verify the characteristics of Korea's military group with MDD and suggest the applicability of PSI and processing speed of K-WAIS-IV as an embedded performance index to test sub-optimal effort or low motivation beyond the purpose of testing cognitive deficits.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.10
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• pp.438-442
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• 2005

Si nanocrystal (Si NC) memory device has several advantages such as better retention, lower operating voltage, reduced punch-through and consequently a smaller cell area, suppressed leakage current. However, the physical and electrical reasons for this behavior are not completely understood but could be related to interface states of Si NCs. In order to find out this effect, we characterized electrical properties of Si NCs embedded in a SiO$_{2}$ layer by scanning probe microscopy (SPM). The Si NCs were generated by the laser ablation method with compressed Si powder and followed by a sharpening oxidation. In this step Si NCs are capped with a thin oxide layer with the thickness of 1$\~$2 nm for isolation and the size control. The size of 51 NCs is in the range of 10$\~$50 m and the density around 10$^{11}$/cm$^{2}$ It also affects the interface states of Si NCs, resulting in the change of electrical properties. Using a conducting tip, the charge was injected directly into each Si NC, and the image contrast change and dC/dV curve shift due to the trapped charges were monitored. The results were compared with C-V characteristics of the conventional MOS capacitor structure.

• The Journal of the Korea Contents Association
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• v.8 no.9
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• pp.42-54
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• 2008

In recent years, embedded systems have been expanding their application domains from traditional embedded systems such as military weapons, robots, satellites and digital convergence systems such as celluar phones, PMP(Portable Multimedia Player), PDAs(Personal Digital Assistants) to Next Generation Personal Computers(NGPCs) such as eating PCs, wearable computers. The NGPCs are network-based, human-centric digital information devices diverged from the traditional PCs used mainly for document writing, internet searching and database management. Wearable computers with battery capacity and memory size limitations have to use real-time operating systems with small footprints and low power management techniques to provide user's QoS in spite of hardware constraints. In this paper, we have designed and implemented a low-power RTOS (called eRTOS) for wearable computers. The implemented eRTOS has 18KB footprints and the dynamic power management and the device power management schemes are adapted in it. Experimental results with wearable computer applications show that the low power techniques could save energy up to 47 %.

• The Journal of the Korea institute of electronic communication sciences
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• v.4 no.1
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• pp.53-59
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• 2009

By the use of open source and 16bit Microcomputer, IDB(Integrated Development Board) for embedded technical education was designed and developed. Based on 16bit MCU H8/300H, LED, LED Matrix, motors, sensors and various I/O circuitry, and the connection to a computer via the SCI, and $16{\times}2$ character LCD was designed and implemented on IDB. In addition, the software development environment was build by the assembler and H8 C compiler which is provided to the open-source software. And memory expansion was considered to include TRON(Real time OS) and uClinux. To verify the developed board, IDB was fabricated by PCB machine, and the fuction was confirmed by the basic I/O control program.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.8
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• pp.75-84
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• 2004

In this paper, we proposed an efficient hardware architecture of line-based lifting algorithm for Motion JPEG2000. We proposed a new architecture of a lifting-based filtering cell which has an optimized and simplified structure. It was implemented in a hardware accommodating both (9,7) and (5,4) filter. Since the output rate is linearly proportional to the input rate, one can obtain the high throughput through parallel operation simply by adding the hardware units. It was implemented into both of ASIC and FPGA The 0.35${\mu}{\textrm}{m}$ CMOS library from Samsung was used for ASIC and Altera was the target for FRGA. In ASIC, the proposed architecture used 41,592 gates for the lifting arithmetic and 128 Kbit memory. For FPGA it used 6,520 LEs(Logic Elements) and 128 ESBs(Embedded System Blocks). The implementations were stably operated in the clock frequency of 128MHz and 52MHz, respectively.