• Title/Summary/Keyword: Embedded IC process

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Large Area Wafer-Level High-Power Electronic Package Using Temporary Bonding and Debonding with Double-Sided Thermal Release Tape (양면 열박리 테이프 기반 임시 접합 공정을 이용한 대면적 웨이퍼 레벨 고출력 전자패키지)

  • Hwang, Yong-Sik;Kang, Il-Suk;Lee, Ga-Won
    • Journal of Sensor Science and Technology
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    • v.31 no.1
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    • pp.36-40
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    • 2022
  • High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

A CMOS IC-Card Interface Chipset (CMOS IC-카드 인터페이스 칩셋)

  • 오원석;이성철;이승은;최종찬
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1141-1144
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    • 2003
  • For proper communication with various types of IC-Card, multiple IC-Card interface complying with the IC-Card standard (ISO7816) is embedded and realized as a peripheral on the 32-bit RISC based system-on-a-chip. It provides the generation of either 3.3V or 5V power supply for the operation of the inserted IC-Card as well. IC-Card interface is divided into an analog front-end (AFE) and a digital back-end (DBE). The embedded DC-DC converters suitable for driving IC-Cards are incorporated in the AFE. The chip design for multiple IC-Card interface is implemented on a standard 0.35${\mu}{\textrm}{m}$ triple-metal double-poly CMOS process and is packaged in a 352-pin plastic ball grid array (PBGA). The total gate count is about 400,000, excluding the internal memory. Die area is 7890${\mu}{\textrm}{m}$ $\times$ 7890${\mu}{\textrm}{m}$.

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Design and Implementation of Embedded Contactless (Type-B) Protocol Module for RFID (RFID를 위한 내장형 비접촉(Type-B) 프로토콜 지원 모듈 설계 및 구현)

  • Jeon, Yong-Sung;Park, Ji-Mann;Ju, Hong-Il;Jun, Sung-Ik
    • The KIPS Transactions:PartA
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    • v.10A no.3
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    • pp.255-260
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    • 2003
  • In recent, as a typical example of RFID, the contactless IC card is widely used in traffic, access control system and so forth. And its use becomes a general tendency more and more because of the development of RF technology and improvement of requirement for user convenience. This paper describes the hardware module to process embedded contactless protocol for implementation contactless IC card. And the hardware module consists of analog circuits and specific digital logic circuits. This paper also describes more effective design method of contactless IC card, which method separates into analog circuit parts, digital logic circuit part, and software parts according to the role of the design parts.

Low Power 260k Color TFT LCD Driver IC

  • Kim, Bo-Sung;Ko, Jae-Su;Lee, Won-Hyo;Park, Kyoung-Won;Hong, Soon-Yang
    • ETRI Journal
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    • v.25 no.5
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    • pp.288-296
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    • 2003
  • In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22 ${\mu}m$ process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.

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LCD Photo-mask Using Commercial LCD Panel (상용 LCD 패널을 이용한 광 마스크 제작)

  • Lee, Seung-Ik;Koh, Jeongh-Hyun;Lee, Sang-Young;Park, Jang-Ho;Soh, Dea-Wha
    • Journal of the Speleological Society of Korea
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    • no.77
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    • pp.21-30
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    • 2007
  • Photo-lithography lies in the middle of the wafer fabrication process. It is often considered as the most critical step in the IC process. We use a mask in exposure steps of the photo-lithography. Typically, 20 to 25 different levels of masks are required to complete an IC device. That means, if a photo process can be developed with the use of only one photo mask, we can reduce more process cost. To satisfy this, we plan to develop an alternative photo mask. For this reason, we chose to use a LCD. We expect to develop a LCD panel that can be changed by electrical control. This is the main idea about the adjustive photo mask. The Photo mask made of LCD panel will replace the former one.

Design of DVB-T/H SiP using IC-embedded PCB Process (IC-임베디드 PCB 공정을 사용한 DVB-T/H SiP 설계)

  • Lee, Tae-Heon;Lee, Jang-Hoon;Yoon, Young-Min;Choi, Seog-Moon;Kim, Chang-Gyun;Song, In-Chae;Kim, Boo-Gyoun;Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.9
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    • pp.14-23
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    • 2010
  • This paper reports the fabrication of a DVB-T/H System in Package (SiP) that is able to receive and process the DVB-T/H signal. The DVB-T/H is the European telecommunication standard for Digital Video Broadcasting (DVB). An IC-embedded Printed Circuit Board (PCB) process, interpose a chip between PCB layers, has applied to the DVB-T/H SiP. The chip inserted in DVB-T/H SiP is the System on Chip (SoC) for mobile TV. It is comprised of a RF block for DVB-T/H RF signal and a digital block to convert received signal to digital signal for an application processor. To operate the DVB-T/H IC, a 3MHz DC-DC converter and LDO are on the DVB-T/H SiP. And a 38.4MHz crystal is used as a clock source. The fabricated DVB-T/H SiP form 4 layers which size is $8mm{\times}8mm$. The DVB-T/H IC is located between 2nd and 3rd layer. According to the result of simulation, the RF signal sensitivity is improved since the layout modification of the ground plane and via. And we confirmed the adjustment of LC value on power transmission is necessary to turn down the noise level in a SiP. Although the size of a DVB-T/H SiP is decreased over 70% than reference module, the power consumption and efficiency is on a par with reference module. The average power consumption is 297mW and the efficiency is 87%. But, the RF signal sensitivity is declined by average 3.8dB. This is caused by the decrease of the RF signal sensitivity which is 2.8dB, because of the noise from the DC-DC converter.

The Embedded 8V-to-12V CMOS DC-DC Converter for a Mobile Battery-Powered System (휴대용 배터리 구동 시스템을 위한 8V-12V 내장형 CMOS DC-DC 컨버터)

  • Oh, Won-Seok;Lee, Seung-Eun;Lee, Sung-Chul;Park, Jin;Choi, Jong-Chan
    • Proceedings of the KIEE Conference
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    • 2002.07d
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    • pp.2577-2579
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    • 2002
  • In this paper, we describe a CMOS DC-DC converter with a variable output voltage(8-12V @100mA) for a portable battery-operated system applications. The proposed DC-DC converter is used along with a Pulse-Frequency Modulation (PFM) method and consists of a reference circuit, a feedback resistor, a controller, and an internal oscillator. The integrated DC-DC converter with two external passive components(L.C) has been designed and fabricated on a 0.6${\mu}m$ 2-poly, 3-metal CMOS process and could be applied to the Personal Digital Assistants(PDA), Cellular Phone, Laptop Computer, etc.

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The Study on Chip Surface Treatment for Embedded PCB (칩내장형 PCB 공정을 위한 칩 표면처리 공정에 관한 연구)

  • Jeon, Byung-Sub;Park, Se-Hoon;Kim, Young-Ho;Kim, Jun-Cheol;Jung, Seung-Boo
    • Journal of the Microelectronics and Packaging Society
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    • v.19 no.3
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    • pp.77-82
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    • 2012
  • In this paper, the research of IC embedded PCB process is carried out. For embedding chips into PCB, solder-balls on chips were etched out and ABF(Ajinomoto Build-ip Film), prepreg and Cu foil was laminated on that to fabricate 6 layer build-up board. The chip of which solder ball was removed was successfully interconnected with PCB by laser drilling and Cu plating. However, de-lamination phenomenon occurred between chip surface and ABF during reflow and thermal shock. To solve this problem, de-smear and plasma treatment was applied to PI(polyimide) passivation layer on chip surface to improve the surface roughness. The properties of chip surface(PI) was investigated in terms of AFM(Atomic Force Micrometer), SEM and XPS (X-ray Photoelectron Spectroscopy). As results, nano-size anchor was evenly formed on PI surface when plasma treatment was combined with de-smear(NaOH+KMnO4) process and it improved thermal shock reliability ($260^{\circ}C$-10sec solder floating).

A Triple-Band Transceiver Module for 2.3/2.5/3.5 GHz Mobile WiMAX Applications

  • Jang, Yeon-Su;Kang, Sung-Chan;Kim, Young-Eil;Lee, Jong-Ryul;Yi, Jae-Hoon;Chun, Kuk-Jin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.11 no.4
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    • pp.295-301
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    • 2011
  • A triple-band transceiver module for 2.3/2.5/3.5 GHz mobile WiMAX, IEEE 802.16e, applications is introduced. The suggested transceiver module consists of RFIC, reconfigurable/multi-resonance MIMO antenna, embedded PCB, mobile WiMAX base band, memory and channel selection front-end module. The RFIC is fabricated in $0.13{\mu}m$ RF CMOS process and has 3.5 dB noise figure(NF) of receiver and 1 dBm maximum power of transmitter with 68-pin QFN package, $8{\times}8\;mm^2$ area. The area reduction of transceiver module is achieved by using embedded PCB which decreases area by 9% of the area of transceiver module with normal PCB. The developed triple-band mobile WiMAX transceiver module is tested by performing radio conformance test(RCT) and measuring carrier to interference plus noise ratio (CINR) and received signal strength indication (RSSI) in each 2.3/2.5/3.5 GHz frequency.

A Study of Machine Learning based Hardware Trojans Detection Mechanisms for FPGAs (FPGA의 Hardware Trojan 대응을 위한 기계학습 기반 탐지 기술 연구)

  • Jang, Jaedong;Cho, Mingi;Seo, Yezee;Jeong, Seyeon;Kwon, Taekyoung
    • Journal of Internet Computing and Services
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    • v.21 no.2
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    • pp.109-119
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    • 2020
  • The FPGAs are semiconductors that can be redesigned after initial fabrication. It is used in various embedded systems such as signal processing, automotive industry, defense and military systems. However, as the complexity of hardware design increases and the design and manufacturing process globalizes, there is a growing concern about hardware trojan inserted into hardware. Many detection methods have been proposed to mitigate this threat. However, existing methods are mostly targeted at IC chips, therefore it is difficult to apply to FPGAs that have different components from IC chips, and there are few detection studies targeting FPGA chips. In this paper, we propose a method to detect hardware trojan by learning the static features of hardware trojan in LUT-level netlist of FPGA using machine learning.