• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.936-939
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• 2002

FPCA is the necessary device to design of hardware at present, it is researched on many ways of applying to design caused by expansion of capacity in recent years. One of these applying ways is SoC (System on a Chip) that is proposed for realizing the basic function of a system. For realizing SoC efficiently, IP (Intellectual property) is very important and developed for re-use of hardware. A MPU for built-in exists as an IP. But almost of MPUs at present as an IPs are lengthy and large-scale for using embedded-application. Furthermore, the function of executing specific treatment critically is required to embedded MPU. We propose a flexible and small scale MPU and its design method.

• 제어로봇시스템학회논문지
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• 제13권1호
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• pp.33-38
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• 2007

In this paper, hardware implementation of interface and control between two robots, the master and the slave robot, are designed. The master robot is the motion capturing device that captures motions of the human operator who wears it. The slave robot is the corresponding humanoid robot arms. Captured motions from the master robot are transferred to the slave robot to follow after the master. All hardware designs such as PID controllers, communications between the master robot, encoder counters, and PWM generators are embedded on a single FPGA chip. Experimental studies are conducted to demonstrate the performance of the FPGA controller design.

• 대한임베디드공학회논문지
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• 제5권2호
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• pp.93-102
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• 2010

The FMCW(Frequency Modulation Continuous Wave) radar possesses range-velocity ambiguity to identify the correct combination of beat frequencies for each target in the multi-target situation. It can lead to ghost targets and missing targets, and it can reduce the detection probability. In this pap er, we propose an effective identification algorithm for the correct pairs of beat frequencies and the signal processing hardware architecture to effectively support the algorithm. First, using the correlation of the detected up- and down-beat frequencies and Doppler frequencies, the possible combinations are determined. Then, final pairing algorithm is completed with the power spectrum density of the correlated up- and down-beat frequencies. The proposed hardware processor has the basic architecture consisting of beat-frequency registers, pairing table memory, and decision unit. This method will be useful to improve the radar detection probability and reduce the false alarm rate.

• Journal of information and communication convergence engineering
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• 제11권2호
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• pp.112-117
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• 2013

In order to reuse a register transfer level (RTL)-based IP block, it takes another architectural exploration in which the RTL will be put, and it also takes virtual platforms to develop the driver and applications software. Due to the increasing demands of new technology, the hardware and software complexity of organizing embedded systems is growing rapidly. Accordingly, the traditional design methodology cannot stand up forever to designing complex devices. In this paper, I introduce an electronic system level (ESL)-based approach to designing complex hardware with a derivative of SystemVerilog. I adopted the concept of reuse with higher levels of abstraction of the ESL language than traditional HDLs to design multiplication server farms. Using the concept of ESL, I successfully implemented server farms as well as a test bench in one simulation environment. It would have cost a number of Verilog/C simulations if I had followed the traditional way, which would have required much more time and effort.

• 대한임베디드공학회논문지
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• 제16권6호
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• pp.253-258
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• 2021

In this paper, we developed a hardware and software platform of the real-time data logging system to verify radar FEM (Front-end Module) and signal-processing algorithms. We developed a hardware platform based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and implemented firmware software to verify the various FEMs. Moreover, we designed PC based software platform to control radar logging parameters and save radar data. The developed platform was verified using 24 GHz multiple channel FMCW (Frequency Modulated Continuous Wave) in an environment of stationary and moving targets of chamber room.

• 대한임베디드공학회논문지
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• 제16권6호
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• pp.313-321
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• 2021

The global market for medical devices is huge, and it will continue showing remarkable growth in the future. However, due to the entry barrier to develop medical devices, many domestic companies have technical problems in entering the medical device industry. In this paper, we introduce an open platform that can help with research and development for companies in the healthcare industry. This open platform consists of a hardware part and a software part. A hardware part is combined into CPU, base and other modules that are easy to replace and assemble. A software part is based on application software for development developed by Bionet. We test the performance of the open medical device platform using a biosignal processing algorithm.

• 대한임베디드공학회논문지
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• 제16권5호
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• pp.233-240
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• 2021

We propose a novel, highly accurate approximate multiplier using different types of inexact 4-2 compressors. The importance of low hardware costs leads us to develop approximate multiplication for error-resilient applications. Several rules are developed when selecting a topology for designing the proposed multiplier. Our highly accurate multiplier design considers the different error characteristics of adopted compressors, which achieves a good error distribution, including a low relative error of 0.02% in the 8-bit multiplication. Our analysis shows that the proposed multiplier significantly reduces power consumption and area by 45% and 26%, compared with the exact multiplier. Notably, a trade-off relationship between error characteristics and hardware costs can be achieved when considering those of existing highly accurate approximate multipliers. In the image blending, edge detection and image sharpening applications, the proposed 8-bit approximate multiplier shows better performance in terms of image quality metrics compared with other highly accurate approximate multipliers.

• 한국멀티미디어학회논문지
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• 제24권12호
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• pp.1653-1662
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• 2021

In this paper, we propose a small waste appliance collection system that can be used for efficient waste appliance collection, and implement an unmanned automatic small waste appliance collector system. First, we collected cases related to the collection of waste home appliances, compared and analyzed methods, and arranged the characteristics. We analyzed at the requirements for the collection and management system of waste appliances by dividing it into the aspect of the discharger and the recycling business company. The collection system consists of a client-server structure, which is a collector system and a collection management server. The unmanned automatic collector system is divided into a control unit and a machine/mechanical unit. We identified the functions that the collector system must perform and the hardware required to perform these functions. Based on this, the collector system was implemented as an embedded system. The hardware and software used in the implementation are described and the implementation results are described. The collection system developed in this paper will contribute to the development of urban mining industry by enabling the efficient collection of waste appliances.

• 대한임베디드공학회논문지
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• 제18권5호
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• pp.249-257
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• 2023

This paper discusses the increasing need for autonomous delivery robots due to the current growth in the delivery market, rising delivery fees, high costs of hiring delivery personnel, and the need for contactless services. Additionally, the cost of hardware and complex software systems required to build and operate autonomous delivery robots is high. To provide a low-cost alternative to this, this paper proposes a autonomous delivery robot platform using a low-cost sensor combination of 2D LIDAR, depth camera and tracking camera to replace the existing expensive 3D LIDAR. The proposed robot was developed using the RTAB-Map SLAM open source package for 2D mapping and overcomes the limitations of low-cost sensors by using the convex hull algorithm. The paper details the hardware and software configuration of the robot and presents the results of driving experiments. The proposed platform has significant potential for various industries, including the delivery and other industries.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.94-97
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• 2002

A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5$\mu\textrm{m}$ CMOS technology, which operates at 58.8MHz with the total CPU load reduced by 57%. It is also verified that the use of the fixed point arithmetic does not incur any significant sound distortion.