Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2002.07a
- /
- Pages.94-97
- /
- 2002
A Hardware Implementation of Ogg Vorbis Audio Decoder with Embedded Processor
- Kosaka, Atsushi (Dept. Inf. Sys. Eng. Osaka University) ;
- Yamaguchi, Satoshi (Dept. Inf. Sys. Eng. Osaka University) ;
- Okuhata, Hiroyuki (Synthesis Corporation) ;
- Onoye, Takao (Dept. Inf. Sys. Eng. Osaka University) ;
- Shirakawa, Isao (Dept. Inf. Sys. Eng. Osaka University)
- Published : 2002.07.01
Abstract
A VLSI architecture of an Ogg Vorbis decoder is proposed : which is dedicated to portable audio appliances. Referring to the computational cost analysis of the decoding processes, the LSP (Line Spectrum Pair) process, which takes more than 50% of the total processing time, can be regarded as a bottleneck to achieve realtime processing by embedded Processors. Thus in our decoder a specific hardware architecture is devised for the LSP process so as to be integrated into a single chip together with an ARM7TDMI processor. In addition, in order to reduce the total hardware cost, instead of the floating point arithmetic, the fixed point arithmetic is adopted. The LSP module has been implemented with 9,740 gates by using a Virtual Silicon 0.l5
Keywords