• 한국정보통신학회:학술대회논문집
• /
• 한국해양정보통신학회 2008년도 추계종합학술대회 B
• /
• pp.571-574
• /
• 2008

본 논문에서는 개선된 회로를 적용한 $256{\times}256$ 픽셀 저항형 지문센서를 제안하고 있다. 단위 픽셀 수준의 센싱 회로는 가변적인 전류를 전압으로 변환하여 이진 디지털 신호로 만든다. 정전기에 효과적으로 대처할 수 있는 인접 픽셀 간 전기적 차폐 레이아웃 구조를 제안하고 있다. 전체회로는 단위 센서 회로를 확장하여 ASIC 설계방식을 통하여 설계한 뒤 로직 및 회로에 대하여 모의실험을 하였다. 전체회로는 $0.35{\mu}m$ 표준 CMOS 공정규칙을 적용하여 센서블록은 전주문 방식을 적용하고 전체 칩은 자동배선 틀을 이용하여 반주문 방식으로 레이아웃을 실시하였다.

• 정보저장시스템학회:학술대회논문집
• /
• 정보저장시스템학회 2005년도 추계학술대회 논문집
• /
• pp.96-102
• /
• 2005

The tribocharge build-up in the slider disk interface can cause ESD (electrostatic discharge) damage. In turn, ESD can cause severe melting damage to MR or GMR heads. We investigated the tribovoltage/current build-up with smooth and textured disks in HDD, operating at increasing disk accelerations. We found that tribe-voltage/current were generated during pico-slider/disk interaction and those levels were about 0.1 ${\~}$ 0.3 V and 10 ${\~}$ 40 pA, respectively. Tribovoltage/current were abruptly increased and dissipated within the acceleration time in the case of textured disk but in the case of smooth disk tribovoltage was continuously increased until the end of uniform velocity region and the tribocurrent did not dissipate within the acceleration time. In the case of textured dist tribovoltage/current was reduced with increasing disk acceleration, but in the case of smooth disk it was increased.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
• /
• pp.82-85
• /
• 2004

This paper proposes an advanced circuit for the capacitive type fingerprint sensor signal processing and an effective isolation structure for minimizing an electrostatic discharge(ESD) influence and for removing a signal coupling noise of each sensor pixel. The proposed detection circuit increases the voltage difference between a ridge and valley about $80\%$ more than old circuit. The test chip is composed of $160\;\times\;192$ array sensing cells $(9,913\times11,666\;um^2).$ The sensor plate area is $58\;\times\;58\;um^2$ and the pitch is 60um. The image resolution is 423 dpi. The chip was fabricated on a 0.35um standard CMOS process. It successfully captured a high-quality fingerprint image and performed the registration and identification processing. The sensing and authentication time is 1 sec(.) with the average power consumption of 10 mW at 3.0V. The reveal ESD tolerance is obtained at the value of 4.5 kV.

• 한국정보통신학회논문지
• /
• 제13권3호
• /
• pp.531-536
• /
• 2009

본 논문에서는 개선된 회로를 적용한 $256{\times}256$ 픽셀 저항형 지문센서를 제안하고 있다. 단위 픽셀 수준의 센싱회로는 가변적인 전류를 전압으로 변환하여 이진 디지털 신호로 만든다. 정전기에 효과적으로 대처할 수 있는 인접 픽셀 간 전기적 차폐 레이아웃 구조를 제안하고 있다. 전체회로는 단위 센서 회로를 확장하여 ASIC 설계방식을 통하여 설계한 뒤 로직 및 회로에 대하여 모의실험을 하였다. 전체회로는 $0.35{\mu}m$ 표준 CMOS 공정규칙을 적용하여 센서블록은 전주문 방식을 적용하고 전체 칩은 자동배선 툴을 이용하여 반주문 방식으로 레이아웃을 실시하였다.

• 한국재료학회지
• /
• 제29권2호
• /
• pp.106-115
• /
• 2019

Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.

• Transactions on Electrical and Electronic Materials
• /
• 제7권1호
• /
• pp.1-6
• /
• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

• 전기학회논문지
• /
• 제63권2호
• /
• pp.319-324
• /
• 2014

The wafer carrier is made of PP, PC, PE resin which have excellent heat and chemical resistance and electrical properties. However, particle generation has become a problem due to static electricity generated in the carrier. Some conductive material such as carbon black (CB) and carbon fiber (CF) are added for the purpose of anti-static, however, additional for motility and particle contamination problems due to high carbon content occurs. In this paper, the electrical characteristics and workability are observed and compared by adding low Carbon Nono Tube(CNT) to each PP, PC and PE resin to solve the problem.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.391-392
• /
• 2008

A SPICE-based 3-dimensional circuit model of Light-Emitting Diode(LED) was modified include the reverse breakdown properties. The new model is found to be accurate to study the failure mechanisms of LEDs under electrostatic discharge (ESD) and electronic overstress (EOS). It was found that the permanent damages under heavy reverse stress is mainly due to the high electric field strength in P-GaN layer.

• 한국전자파학회논문지
• /
• 제28권5호
• /
• pp.366-372
• /
• 2017

본 논문에서 제시하는 내용은 수신단의 관문 역할을 담당하는 차동 저 잡음 증폭기를 구현 시, 필연적으로 설계가 필요한 발룬에 대한 분석 내용이다. 발룬은 안테나로부터 입력된 단일 신호를 차동 신호로 변환시켜줌으로써 차동 증폭기의 입력으로 사용될 수 있도록 하는 역할을 담당한다. 이 뿐만 아니라, 안테나를 통해서 들어오는 ESD(Electrostatic Discharge)로부터 회로를 보호하고, 입력 정합에 도움을 준다. 하지만, 일반적으로 사용되는 수동형 발룬의 경우, 두 금속선 사이에 형성되는 전자기적 결합을 통해 교류 신호를 전달하는 방식이므로 이득없이 손실을 가지게 될 뿐 아니라 결론적으로 수신단 전체 잡음 지수 저하에 가장 큰 영향을 미치게 된다. 그러므로, 저 잡음 증폭기에서 발룬의 설계는 매우 중요하며, 선로의 폭, 선로 간격, 권선수, 반경, 그리고 레이아웃의 대칭 구조 등을 고려하여 높은 양호도(quality factor)와 차동 신호의 역위상을 만들어내야만 한다. 본문에서 발룬의 양호도를 높이기 위해 고려해야할 요소들을 정리하고, 설계 요소변경에 따른 발룬의 저항, 인덕턴스, 그리고 캐패시턴스의 변화 경향성을 분석하였다. 분석 결과를 바탕으로 입력 발룬을 설계함으로써 이득 24 dB, 잡음 지수 2.51 dB의 저잡음, 고 이득 차동 증폭기 설계가 가능함을 증명하였다.

• Tribology and Lubricants
• /
• 제22권2호
• /
• pp.59-65
• /
• 2006

In hard disk drives as the head to disk spacing continues to decrease to facilitate recording densities, slider disk interactions have become much more severe due to direct contact of head and disk surfaces in both start/stop and flying cases. The slider disk interaction in CSS (contact-start-stop) mode is an important source of particle generation and tribocharge build-up. The tribocharge build-up in the slider disk interface can cause ESD (electrostatic discharge) damage. In turn, ESD can cause severe melting damage to MR or GMR heads. The spindle speed of typical hard disk drives has increased in recent years from 5400 rpm to 15000 rpm and even higher speeds are anticipated in the near future. And the increasing disk velocity leads to increasing disk acceleration and this might affect the tribocharging phenomena of the slider/disk interface. We investigated the tribocurrent/voltage build-up generated in HDD, operating at increasing disk accelerations. In addition, we examined the effects with relative humidity conditions and rest time. We found that the tribocurrent/voltage was generated during pico-slider/disk interaction and its level was about $3\sim16pA$ and $0.1\sim0.3V$, respectively. Tribocurrent/voltage build-up was reduced with increasing disk acceleration. Higher humidity conditions $(75\sim80%)$ produced lower levels tribovoltage/current. Therefore, a higher tribocharge is expected at a lower disk acceleration and lower relative humidity condition. Rest time affected the charge build-up at the slider-disk interface. The degree of tribocharge build-up increased with increasing rest time.