• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 A
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• pp.237-239
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• 2001

This paper describes the digital relay simulator system using digital signal processor. The simulator system has two parts, one is software and the other is hardware part. The simulation software has variety calculation engines ; EMTP simulation data file conversion, user define simulation data generation, sequence data generation, data analysis engines. etc, these are designed upon GUI. And simulator software provides easy control interface for users, the simulator software performs on every MS Windows OS. The simulator hardware design uses 32bit floating point DSP(TMS320C32) architecture to achieve flexibility and high speed operation.

• 한국철도학회논문집
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• 제5권2호
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• pp.104-111
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• 2002

The purpose of interlocking system was to prevent the route for a train being set up and its protecting signal cleared if there was already another, conflicting route set up and the protecting signal for that route cleared. This paper proposed Interlocking Inspection System(IIS) consisting of interlocking simulator and field simulator to operate interlocking test of computer based Electronic Interlocking System(EIS) in this paper. Interlocking simulator consists of Design Edit System(DES), Logical Database Management Tool(LDMT) and real-time confirming system, field simulator is a equipment to simulate a control object of EIS and constitutes configuration operated in 19 inch standard rack. As a result of test to prove capacity of this IIS, the efficiency was shown as excellent. Therefore by using inspection system, we obtain every advantages. It has the functions for test data generation and automatic test execution based on personal computer. Time and cost for test work can be reduced more efficiently by using this developed inspection system

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.48-52
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• 2014

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.231-232
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• 2006

In this paper, we developed a simulator for the DVB-T which can predict the performance of the system. In the simulator, the transmitter and receiver are implemented based on the European standard of the DVB-T. The BER performance is measured for various QAM levels and coding rates in Rician channels with several mobile speeds.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1121-1122
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• 2008

By using FACS(Facial Action Coding System) and linear interpolation, a 3D facial robot simulator is developed in this paper. This simulator is based on real facial robot and synchronizes with it by unifying protocol. Using AUs(Action Unit) of each 5 basic expressions and linear interpolation makes more various dynamic facial expressions.

• 대한의용생체공학회:의공학회지
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• 제30권1호
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• pp.94-102
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• 2009

In this paper, we propose a hearing impairment simulator considering reduced frequency selectivity of the hearing impaired, and verify it's performance through experiments. The reduced frequency selectivity was embodied by spectral smearing using linear prediction coding(LPC). The experiments are composed of 4 kinds of tests; pure tone test, speech reception threshold(SRT) test, and word recognition score(WRS) test without spectral smearing and with spectral smearing. The experiments of the hearing impairment simulator were performed with 9 subjects who have normal hearing. The amount of spectral smearing was controlled by LPC order. The percentile score of WRS test without smearing is $89.78{\pm}2.420%$. The scores of WRS with 24th LPC order and with 8th LPC order are $88.00{\pm}3.556%$ and $83.78{\pm}2.123%$ respectively. It is verified that WRS score is lowered by decreasing LPC order. This is a reasonable result considering that spectral smearing is getting heavier according to decreasing LPC order. It is confirmed that spectral smearing using LPC simulates the reduced frequency selectivity of the hearing impaired and affects the clearness of speech reception.

• 조명전기설비학회논문지
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• 제16권2호
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• pp.1-8
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• 2002

전자식 안정기는 자기식 안정기에 비해서 고주파로 점등하기 때문에 방전등에서 나타나는 음향 공명 현상으로 인한 Arc의 떨림이 나타날 수는 있으나 소형, 경량화 및 조광 기능을 가질 수 있음으로 인해서 그 응용분야가 더욱 더 넓어지고 있다. 본 논문에서는 일반적으로 글 알려져 있는 수은 램프 모델링을 응용하여 메탈 할라이드 램프의 모델링을 만들고램프에서 발생하는 음향 공명 현상을 해소하기 위해 음향 공명의 영향을 반지 않는 동작 주파수를 설정하였다. 또한 새로운 방법의 출력 회로(LCC)의 선계 방법을 다루었다. 또한 SIMULINK를 이용하여 메탈할라이드 램프를 사용한 전자식 안정기 시물레이터를 제작하였고, 이를 통해서 쉽게 인버터 출력부LCC값을 결정하였고 시뮬레이션 특성은 실제 안정기를 제작한 후 결과 값을 비교함으로써 시뮬레이터 특성을 검증하였다.

• 전기학회논문지P
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• 제53권2호
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• pp.70-76
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• 2004

The purpose of interlocking system in railway is to prevent the route for a train being set up and its protecting signal cleared if there were already another, conflicting route set up and the protecting signal for that route cleared. Recently, conventional relays circuitry in industrial field is replaced to computer-based control systems according to the advance of computer and communication technology. Therefore, interlocking systems in railway field are rapidly changing from existing relay-based interlocking system to computer-based electronic ones that executes the vital interlocking logic to assure the safety train routes at trackside signaling equipment room using electronic circuits. So it is very important to verify the performance of developed electronic interlocking system by plentiful laboratory testing before actually application in the railway system. However the laboratory testing in the present state of railway signaling is preformed individually by manual, so very much test time and cost are required. To solve these problems, we are developed the simulator for automatic interlocking inspection in this research. This simulator is able to operate on general personal computer and has following beneficial functions : automatic test sheet generation for inspection, automatic inspection execution and et al. The experiments are executed to test the feasibility of the developed simulator the experimental results have good agreements with the anticipated ones.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.248-251
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• 2000

The ATM-PON is regarded as an effective access network because the system transmits the various user's information through the passive optical splitter in a single platform. The ranging technology is to place all ONUs at the same distance virtually in order to form ATM-PON based on the Time Division Multiplexing (TDM). In This paper, We show the steps about ranging protocol based on ITU-T G.983.1 and ranging procedure modeling. Also, We implement the simulator that considers various environments to verify the time specifications of G.983.1. By using the simulator, We find out the wasted bandwidth which influences active ONUs during the ranging procedure.

• 한국정보처리학회논문지
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• 제2권4호
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• pp.603-610
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• 1995

본 논문에서는 함수 기능에서 로직 게이트 기능까지 시뮬레이션 가능한 고성능의 로직 시뮬레이터(HSIM) 개발에 대해서 논한다. 개발된 로직 시뮬레이터는 입력부, 시 뮬레이터 본체, 출력부로 구성되어 있으며, 입력부에는 네트 리스트 컴파일러, 부품 정보 컴파일러가 포함된다. 시뮬레이터 본체에는 시뮬레이션 속도를 높이기 위한 각종 기술과 시뮬레이터의 중심 부분인 시뮬레이션 엔진 등이 소속되어 있다. 출력부에는 시뮬레이션 결과를 분석하는 파형 분석기가 있다. 개발된 시뮬레이터 본체의 주요 특 징은 점진적 로더를 사용하여 컴파일된 부품 기능들을 시뮬레이션 엔진에서 직접 로드 하여 시뮬레이션을 수행한다. 이렇게 한 결과 기존의 유릿 딜레어 event-driven interpretive 시뮬레이터와 비교했을 때 55% 이상 속도가 빠른 효과적인 성능 향상을 달성했다.