• Transactions of Materials Processing
• /
• v.11 no.7
• /
• pp.614-619
• /
• 2002

For an accurate measurement of the material behavior of small structures, a new optical experimental technique is proposed to measure the deformation. The test method uses the dual microscope that can measure the relative deformation of two adjacent regions. The magnified view is captured by CCD cameras and the relative deformation can be measured by the pattern matching and tracing method. Using this experimental technique, the deformation of solder joints in electronic packaging and the strain of the nickel thin film are measured.

• Journal of the Microelectronics and Packaging Society
• /
• v.20 no.3
• /
• pp.23-29
• /
• 2013

Development of flexible electronic devices has primarily focused on printing technology using organic materials. However, organic-based flexible electronics have several disadvantages, including low electrical performance and long-term reliability. Therefore, we fabricated nano- and micro-thick silicon film attached to the polymer substrate using transfer printing technology to investigate the feasibility of silicon-based flexible electronic devices with high performance and high flexibility. Flexibility of the fabricated samples was investigated using bending and stretching tests. The failure bending radius of the 200 nm-thick silicon film attached on a PI substrate was 4.5 mm, and the failure stretching strain was 1.8%. The failure bending radius of the micro-thick silicon film attached on a FPCB was 2 mm, and the failure strain was 3.5%, which showed superior flexibility compared with conventional silicon material. Improved flexibility was attributed to a buffering effect of the adhesive between the silicon film and the substrate. The superior flexibility of the thin silicon film demonstrates the possibility for flexible electronic devices with high performance.

• Journal of the Microelectronics and Packaging Society
• /
• v.22 no.1
• /
• pp.69-74
• /
• 2015

With difficulties during the cleaning of reflow flux residues due to the decrease of the part size and interconnection pitch in the advanced electronic devices, the need for the no-clean solder paste is increasing. In this study, an epoxy curable solder paste was made with SAC305 solder powder and the curable flux of which the main ingredient is epoxy resin and its reflow solderability, flux residue corrosivity and solder joint mechanical properties was investigated with comparison to the commercial rosin type solder paste. The fillet shape of the cured product around the reflowed solder joint revealed that the curing reaction occurred following the fluxing reaction and solder joint formation. The copper plate solderability test result also revealed that the wettability of the epoxy curable solder paste was comparable to those of the commercial rosin type solder pastes. In the highly accelerated temperature and humidity test, the cured product residue of the curable solder paste showed no corrosion of copper plate. From FT-IR analysis, it was considered to be resulted from the formation of tight bond through epoxy curing reaction. Ball shear, ball pull and die shear tests revealed that the adhesive bonding was formed with the solder surface and the increase of die shear strength of about 15~40% was achieved. It was considered that the epoxy curable solder paste could contribute to the improvement of the package reliability as well as the removal of the flux residue cleaning process.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.3
• /
• pp.89-93
• /
• 2020

Complex warpage behavior of the electronic packages causes internal stress so many kinds of mechanical failure occur such as delamination or crack. Efforts to predict the warpage behavior accurately in order to prevent the decrease in yield have been approached from various aspects. For warpage prediction, silicon is generally treated as a homogeneous material, therefore it is described as showing no warpage behavior due to thermal loading. However, it was reported that warpage is actually caused by residual stress accumulated during grinding and polishing in order to make silicon wafer thinner, which make silicon wafer inhomogeneous through thickness direction. In this paper, warpage behavior of the single-side polished wafer at solder reflow temperature, the highest temperature in packaging processes, was measured using 3D digital image correlation (DIC) method. Mechanism was verified by measuring coefficient of thermal expansion (CTE) of both mirror-polished surface and rough surface.

• KOREAN JOURNAL OF PACKAGING SCIENCE & TECHNOLOGY
• /
• v.29 no.3
• /
• pp.223-228
• /
• 2023

Sustainable energy supplies without the recharging and replacement of the charge storage device have become increasingly important. Among various energy harvesters, the triboelectric nanogenerator (TENG) has attracted considerable attention due to its high instantaneous output power, broad selection of available materials, eco-friendly and inexpensive fabrication process, and various working modes customized for target applications. In this study, the amount of voltage and current generated was measured by applying the PSD profile random vibration test of the electronic vibration tester and ISTA 3A according to the time of Anodized Aluminum Oxide (AAO) pore widening of the manufactured TENG device Teflon and AAO. The discharge and charging tests of the integrated module during the random simulated transport environment and the recognition distance of RFID were measured while agricultural products (onion) were loaded into the returnable folding plastic box. As a result, it was found that AAO alumina etching processing time to maximize TENG performance was optimal at 31 min in terms of voltage and current generation, and the integrated module applied with the TENG module showed a charging effect even during the continuous use of RFID, so the voltage was kept constant without discharge. In addition, the RFID recognition distance of the integrated module was measured as a maximum of 1.4 m. Therefore, it was found that the surface condition of AAO, a TENG element, has a great influence on the power generation of the integrated module, and due to the characteristics of TENG, the power generation increases as the surface dries, so it is judged that the power generation can be increased if the surface drying treatment (ozone treatment, etc.) of AAO is applied in the future.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.1 s.34
• /
• pp.35-40
• /
• 2005

The oxidation of pure Sn and Sn-0.7Cu, Sn-3.5Ag, Sn-lZn, and Sn-9Zn alloys at $150^{\circ}C$ was investigated. Both the chemical nature and the amount of oxides were characterized using electrochemical reduction analysis by measuring the electrolytic reduction potential and total transferred electrical charges. X-ray photoelectron spectroscopy (XPS) was also conducted to support the results of reduction analysis. The effect of Cu, Ag and Zn addition on surface oxidation of Sn alloys is reported. For Sn, Sn-0.7Cu and Sn-3.5Ag, SnO grew first and then the mixture of SnO and $SnO_2$ was found. $SnO_2$ grew predominantly for a long-time aging. For Zn containing Sn alloys, both ZnO and $SnO_2$ were formed. Zn promotes the formation of $SnO_2$. Sn oxide growth rate of Pb-free solder alloys was also discussed in terms of alloying elements.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.3
• /
• pp.43-48
• /
• 2012

Errors of relative permittivity calculation caused by the variation of sample aspect ratio (diameter/height) and measuring geometry were analyzed by computer simulation and measurement. Firstly, the $S_{21}$ spectrum of the sample (permittivity 38) was simulated in the post resonator measuring apparatus by HFSS simulation. Then, the relative permittivity was calculated from the $TE_{011}$ mode resonant frequency. The relative permittivity varied by ca. 0.3% with sample aspect ratio variation (D/H=0.8~1.6). The relative permittivity varied by ca. 1~10% when the 1~10% of air-gap was introduced in between the dielectric disk and upper conductor. All the simulation results showed consistent tendency with real measurement.

• Journal of the Microelectronics and Packaging Society
• /
• v.19 no.3
• /
• pp.9-14
• /
• 2012

Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.3 s.333
• /
• pp.17-24
• /
• 2005

We fabricated PIN-Photodiodes with a single mode fiber for analog communications and analyzed characteristics of the devices. The fabricated PIN-Photodiode shows a bandwidth of 1.5 GHz, a dark current of 20 p4 a capacitance of 0.48 pF, and the responsivity of 0.9 V/W, a second order distortion of -72 dBc. In this paper, we developed a new optical Packaging technology that is aligning in real-time monitoring of both responsivity and IM2 characteristics. As a result responsivity has been improved by 0.03 V/W, and also U has been improved by $3\~5\;dBc$. On the other hand, failure ratio has been reduced by $3.5\%$.

• Journal of the Microelectronics and Packaging Society
• /
• v.21 no.4
• /
• pp.63-68
• /
• 2014

For a nanoscale Cu/low-k wafer, inter-layer dielectric (ILD) and metal layers peelings, cracks, chipping, and delamination are the most common dicing defects by traditional diamond blade saw process. Sidewall void in sawing street is one of the key factors to bring about cracks and chipping. The aim of this research is to evaluate laser grooving & mechanical sawing parameters to eliminate sidewall void and avoid top-side chipping as well as peeling. An ultra-fast pico-second (ps) laser is applied to groove/singulate the 28-nanometer node wafer with Cu/low-k dielectric. A series of comprehensive parametric study on the recipes of input laser power, repetition rate, grooving speed, defocus amount and street index has been conducted to improve the quality of dicing process. The effects of the laser kerf geometry, grooving edge quality and defects are evaluated by using scanning electron microscopy (SEM) and focused ion beam (FIB). Experimental results have shown that the laser grooving technique is capable to improve the quality and yield issues on Cu/low-k wafer dicing process.