• Korean Journal of Materials Research
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• v.22 no.7
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.411-418
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• 2011

The current study investigates the electroplating characteristics of Sn-Cu eutectic micro-bumps electroplated on a Si chip for flip chip application. Under bump metallization (UBM) layers consisting of Cr, Cu, Ni and Au sequentially from bottom to top with the aim of achieving Sn-Cu bumps $10\times10\times6$ ${\mu}m$ in size, with 20${\mu}m$ pitch. In order to determine optimal plating parameters, the polarization curve, current density and plating time were analyzed. Experimental results showed the equilibrium potential from the Sn-Cu polarization curve is -0.465 V, which is attained when Sn-Cu electro-deposition occurred. The thickness of the electroplated bumps increased with rising current density and plating time up to 20 mA/$cm^2$ and 30 min respectively. The near eutectic composition of the Sn-0.72wt%Cu bump was obtained by plating at 10 mA/$cm^2$ for 20 min, and the bump size at these conditions was $10\times10\times6$ ${\mu}m$. The shear strength of the eutectic Sn-Cu bump was 9.0 gf when the shearing tip height was 50% of the bump height.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.40 no.11
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• pp.755-759
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• 2016

The use of heat pipes in the electronic telecommunication field is increasing. Among the various types of heat pipes, the thin flat heat pipe has relatively high applicability compared with the circular heat pipe in the electronic packaging application. The thin flat heat pipe based on extrusion fabrication has a simple capillary wick structure consisting of rectangular cross sectional grooves on the inner wall of the pipe. Although the groove serves as a simple capillary wick, and many such grooves are provided on the inner wall, it is difficult for the grooves to realize a sufficiently high capillary force. In the present study, a thin flat heat pipe with a wire bundle was developed to overcome the drawback of poor capillary force in the thin flat heat pipe with grooves, and was evaluated by conducting tests. In the performance test, the thin flat heat pipe with the wire bundle showed a lower thermal resistance of approximately 3.4 times, and a higher heat transfer rate of approximately 3.8 times with respect to the thin flat heat pipe with grooves as the capillary wick respectively. The possibility of using the wire bundle as a capillary wick in the heat pipe was validated in the present study; further study for commercializing this concept will be taken up in the future.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.6
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• pp.526-534
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• 2011

The MFS (Mlti-Functional Structure) concept, which integrates the electronics, thermal control and structure into a single packaging system, has been developed and applied to reduce the volume and weight of the satellite. Therefore, this MFS can eliminate the bulky chassis/frames, cables and connectors of the electronic equipment. The main point of this traditional MFS is the replacement of the electrical chassis/frames with MCMs (Multi-Chip Modules) that require much costs and efforts for developing. This paper shows the new MFS concept that effectively saves the volume and weight. The structure including the thermal control and radiation shielding elements will be designed and manufactured as the rectangular grid-stiffened structure. The rectangular grid-stiffened structure is the modification of the iso-grid structure, and provides the enough spaces for putting the general PCBs without the chassis/frames.

• Membrane Journal
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• v.27 no.2
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• pp.154-166
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• 2017

Polymeric films for gas barrier applications such as food packaging and electronic devices have attracted great interest due to their cheap, light and easy processability among gas barrier materials. Especially in electronic devices, extremely low gas permeance is necessary for maintaining the device performance. However, current polymeric barrier films still suffer from relatively high gas permeance than other materials. Therefore, there have been strong needs to enhance the gas barrier performance of polymeric barrier films while keep their own advantages. Recently, graphene is highlighted as a 2D-layered material for gas barrier applications. However, owing to the poor workability and difficulty to produce in engineering scale, graphene oxide (GO) is on the rise. GO consists of oxygen-containing functional groups on surface with intrinsic 2D-layered structure and high aspect ratio, and it can be well-dispersed in aqueous polar solvents like water, resulting in scalable mass production. Here, we prepared GO incorporated polyimide (PI) nanocomposites. PI is widely used barrier polymer with high mechanical strength and thermal and chemical stability. We demonstrated that PI/GO nanocomposites could perform as a gas barrier. Furthermore, surfactants (Triton X-100 (TX) and Sodium deoxycholate (SDC)) are introduced to enhance the gas barrier performance by improving the degree of dispersion of GO in PI matrix. As a result, TX enhanced the gas barrier performance of PI/GO nanocomposites which is similar to predicted value. This finding will provide new insight to polymer nanocomposites for gas barrier applications.

• Journal of the Korean Society of Food Science and Nutrition
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• v.40 no.9
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• pp.1307-1313
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• 2011

This study was conducted to evaluate the effects of irradiation temperature on the physicochemical and sensory properties of Tarakjuk, milk porridge. Tarakjuk was gamma-irradiated at different temperatures of $25^{\circ}C$ (in room), $4^{\circ}C$ (in ice), and $-20^{\circ}C$ (in dry ice) at a dose of 10 kGy, and then autoclaved at $120^{\circ}C$ for 15 min for comparison. pH and Hunter's color value of Tarakjuk were not changed by irradiation regardless of the temperature. However, the TBA (2-thiobarbituric acid) value decreased as irradiation temperature was decreased. The viscosity of Tarakjuk irradiated in dry ice was significantly higher than that irradiated at room temperature and in ice (p<0.05). For the sensory evaluation, there were no significant differences in overall acceptability between non-treated Tarakjuk and that irradiated in dry ice. Flavor pattern analysis using an electronic nose with a SAW (surface acoustic wave) sensor determined that the main peaks at retention times 3.88 and 7.34 sec were related with off-flavor induced by irradiation and unique flavor of Tarakjuk, respectively. These results indicated that irradiation at freezing temperature improved quality deterioration of Tarakjuk by gamma irradiation. However, sensory quality of Tarakjuk irradiated at freezing temperature was still lower than that of non-irradiated Tarakjuk. Therefore, further research is needed to improve the quality of Tarakjuk using combined treatment such as addition of antioxidants and vacuum packaging method.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.3
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• pp.130-134
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• 2018

In the past few years, various solder compositions have been a representative material to electronic packages and surface mount technology industries as a replacement of Pb-base solder alloy. Therefore, extensive studies on process and/or reliability related with the low Ag composition have been reported because of recent rapid rise in Ag price. In this study, Sn-3.0Ag-0.5Cu, Sn-0.7Cu and Sn-0.3Ag-0.5Cu solder bar samples were fabricated by melting of Sn, Ag and Cu metal powders. Crystal structure and element concentration were analyzed by XRD, XRF, optical microscope, FE-SEM and EDS. The fabricated solder samples were composed of ${\beta}-Sn$, ${\varepsilon}-Ag_3Sn$ and ${\eta}-Cu_6Sn_5$ phases.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.