• Title/Summary/Keyword: Electronic package

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EFFECTS OF PROCESS INDUCED DEFECTS ON THERMAL PERFORMANCE OF FLIP CHIP PACKAGE

  • Park, Joohyuk;Sham, Man-Lung
    • Proceedings of the International Microelectronics And Packaging Society Conference
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    • 2002.11a
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    • pp.39-47
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    • 2002
  • Heat is always the root of stress acting upon the electronic package, regardless of the heat due to the device itself during operation or working under the adverse environment. Due to the significant mismatch in coefficient of thermal expansion (CTE) and the thermal conductivity (K) of the packaging components, on one hand intensive research has been conducted in order to enhance the device reliability by minimizing the mechanical stressing and deformation within the package. On the other hand the effectiveness of different thermal enhancements are pursued to dissipate the heat to avoid the overheating of the device. However, the interactions between the thermal-mechanical loading has not yet been address fully. in articular when the temperature gradient is considered within the package. To address the interactions between the thermal loading upon the mechanical stressing condition. coupled-field analysis is performed to account the interaction between the thermal and mechanical stress distribution. Furthermore, process induced defects are also incorporated into the analysis to determine the effects on thermal conducting path as well as the mechanical stress distribution. It is concluded that it feasible to consider the thermal gradient within the package accompanied with the mechanical analysis, and the subsequent effects of the inherent defects on the overall structural integrity of the package are discussed.

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Electrical Parameter Extraction of High Performance Package Using PEEC Method

  • Pu, Bo;Lee, Jung-Sang;Nah, Wan-Soo
    • Journal of electromagnetic engineering and science
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    • v.11 no.1
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    • pp.62-69
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    • 2011
  • This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

Acceleration Test for Package of High Power Phosphor Converted White Light Emitting Diodes (고출력 형광체변환 백색 LED 패키지의 가속시험)

  • Chan, Sung-Il;Yu, Yang-Gi;Jang, Joong-Soon
    • Journal of Applied Reliability
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    • v.10 no.2
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    • pp.137-148
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    • 2010
  • This study deals with the accelerated life test of high power phosphor converted white Light Emitting Diodes (High power LEDs). Samples were aged at $110^{\circ}C$/85% RH and $130^{\circ}C$/85% RH up to 900 hours under non-biased condition. The stress induced a luminous flux decay on LEDs in all the conditions. Aged devices exhibited modification of package silicon color from white to yellowish brown. The instability of the package contributes to the overall degradation of optical lens and structural degradations such as generating bubbles. The degradation mechanisms of lumen decay and reduction of spectrum intensity were ascribed to hygro-mechanical stress which results in package instabilities.

Wafer Level Packaging of RF-MEMS Devices with Vertical Feed-through (수직형 Feed-through 갖는 RF-MEMS 소자의 웨이퍼 레벨 패키징)

  • Park, Yun-Kwon;Lee, Duck-Jung;Park, Heung-Woo;kim, Hoon;Lee, Yun-Hi;Kim, Chul-Ju;Ju, Byeong-Kwon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.15 no.10
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    • pp.889-895
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    • 2002
  • Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

Radio Frequency Circuit Module BGA(Ball Grid Array) (Radio Frequency 회로 모듈 BGA(Ball Grid Array) 패키지)

  • Kim, Dong-Young;Jung, Tae-Ho;Choi, Soon-Shin;Jee, Yong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.1
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    • pp.8-18
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    • 2000
  • We presented a BGA(Ball Grid Array) package for RF circuit modules and extracted its electrical parameters. As the frequency of RF system devices increases, the effect of its electrical parasitics in the wireless communication system requires new structure of RF circuit modules because of its needs to be considered of electrical performance for minimization and module mobility. RF circuit modules with BGA packages can provide some advantages such as minimization, shorter circuit routing, and noise improvement by reducing electrical noise affected to analog and digital mixed circuits, etc. We constructed a BGA package of ITS(Intelligent Transportation System) RF module and measured electrical parameters with a TDR(Time Domain Reflectometry) equipment and compared its electrical parasitic parameters with PCB RF circuits. With a BGA substrate of 3${\times}$3 input and output terminals, we have found that self capacitance of BGA solder ball is 68.6fF, and self inductance 146pH, whose values were reduced to 34% and 47% of the value of QFP package structure. S11 parameter measurement with a HP4396B Network Analyzer showed the resonance frequency of 1.55GHz and the loss of 0.26dB. Routing length of the substrate was reduced to 39.8mm. Thus, we may improve electrical performance when we use BGA package structures in the design of RF circuit modules.

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