• Elastomers and Composites
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• v.59 no.2
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• pp.73-81
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• 2024

In the field of electronic components, the potting material, which is a part of the electronic circuit package, plays a significant role in protecting circuits from the external environment and reducing signal interference among electronic devices during operation. This significantly affects the reliability of the components. Therefore, the accurate prediction and assessment of the lifespan of a material are of paramount importance in the electronics industry. We conducted an accelerated thermal aging evaluation using the Arrhenius technique on elastic potting material developed in-house, focusing on its insulation, waterproofing, and contraction properties. Through a comprehensive analysis of these properties and their interrelations, we confirmed the primary factors influencing molding material failure, as increased hardness is related to aggregation, adhesion, and post-hardening or thermal-aging-induced contraction. Furthermore, when plotting failure times against temperature, we observed that the hardness, adhesive strength, and water absorption rate were the predominant factors up to 120 ℃. Beyond this temperature, the tensile properties were the primary contributing factors. In contrast, the dielectric constant and loss tangent, which are vital for reducing signal interference in electric devices, exhibited positive changes(decreases) with aging and could be excluded as failure factors. Our findings establish valuable correlations between physical properties and techniques for the accurate prediction of failure time, with broad implications for future product lifespans. This study is particularly advantageous for advancing elastic potting materials to satisfy the stringent requirements of reliable environments.

• The Korean Journal of Archival Studies
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• no.16
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• pp.39-96
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• 2007

Traditionally, the concept of transfer is that physical records such as paper documents, videos, photos are made a delivery to Archives or Records centers on the basis of transfer guidelines. But, with the automation of records management environment and spreading new records creation and management applications, we can create records and manage them in the cyberspace. In these reasons, the existing transfer system is that we move filed records to Archives or Records centers by paper boxes, needs to be changed. Under the needing conditions of a new transfer paradigm, the fact that the revision of Records Act that include some provisions about electronic records management and transfer, is desirable and proper. Nevertheless, the electronic transfer provisions are too conceptional to apply records management practice, so we have to develop detailed methods and processes. In this context, this paper suggest that a electronic records transfer process model on the basis of international standard and foreign countries' cases. Doing transfer records is one of the records management courses to use valuable records in the future. So, both producer and archive have to transfer records itself and context information to long-term preservation repository according to the transfer guidelines. In the long run, transfer comes to be the conclusion that records are moved to archive by a formal transfer process with taking a proper records protection steps. To accomplish these purposes, I analyzed the 'OAIS Reference Model' and 'Producer-Archive Interface Methodology Abstract Standard-CCSDS Blue Book' which is made by CCSDS(Consultative committee for Space Data Systems). but from both the words of 'Reference Model' and 'Standard', we can understand that these standard are not suitable for applying business practice directly. To solve this problem, I also analyzed foreign countries' transfer cases. Through the analysis of theory and case, I suggest that an Electronic Records Transfer Process Model which is consist of five sub-process that are 'Ingest prepare ${\rightarrow}$ Ingest ${\rightarrow}$ Validation ${\rightarrow}$ Preservation ${\rightarrow}$ Archival storage' and each sub-process also have some transfer elements. Especially, to confirm the new process model's feasibility, after classifying two types - one is from Public Records center to Public Archive, the other is from Civil Records center to Public or Civil Archive - of Korean Transfer, I made the new Transfer Model applied to the two types of transfer cases.

• Journal of the Microelectronics and Packaging Society
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• v.10 no.1
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• pp.31-38
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• 2003

In the current electronic technology atmosphere, MEMS (Microelectromechanical System) technology is regarded as one of promising device manufacturing technologies to realize market-demanding device properties. In the packaging of MEMS devices, the packaged structure must maintain hermeticity to protect the devices from a hostile atmosphere during their operations. For such MEMS device vacuum packaging, we introduce the LTCC (Low temperature Cofired Ceramic) packaging technology, in which embedded passive components such as resistors, capacitors and inductors can be realized inside the package. The technology has also the advantages of the shortened length of inner and surface traces, reduced signal delay time due to the multilayer structure and cost reduction by more simplified packaging processes owing to the realization of embedded passives which in turn enhances the electrical performance and increases the reliability of the packages. In this paper, the leakage rate of the LTCC package having several interfaces was measured and the possibility of LTCC technology application to MEMS devices vacuum packaging was investigated and it was verified that improved hermetic sealing can be achieved for various model structures having different types of interfaces (leak rate: stacked via; $4.1{\pm}1.11{\times}10^{-12}$/ Torrl/sec, LTCC/AgPd/solder/Cu-tube; $3.4{\pm}0.33{\times}10^{-12}$/ Torrl/sec). In real application of the LTCC technology, the technology can be successfully applied to the vacuum packaging of the Infrared Sensor Array and the images of light-up lamp through the sensor way in LTCC package structure was presented.

• Korean Journal of Optics and Photonics
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• v.18 no.4
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• pp.264-269
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• 2007

Today's research has been focused on changing the light source from filament to LED for luminarie illumination to overcome the shortcoming of a filament. The purpose of this research is to make an appropriate high power LED package structure for luminarie. We simulated radiation patterns of the various structures by the ray tracing simulator (Light Tools), and also analyzed the radiation patterns using an LED test system (OL770). As we increased an inner reflector angle, the radiation pattern split into two peaks and the angle between two peaks became larger. In addition, when we increased an outer reflector angle, the angle between side peaks gradually decreased, while it increased again when the angle reach $50^{\circ}$. These results could be understood from the ray tracing of the light reflected from two reflectors. We made the high power LED package for luminarie on the condition of the optimized structure which was made by ray tracing simulation results, and we measured the radiation patterns by using an LED test system, and these results were well matched to the simulation results.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.2 s.35
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• pp.111-119
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• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.37-44
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• 2013

It is well known that thermal deformation of electronic packages with Pb-Sn solder and with lead-free solder is significantly affected by material properties consisting the package, as well as those of the solder itself. In this paper, the method for determining coefficient of thermal expansion(CTE) of new material is established by using temperature characteristic of strain gages, and the CTE of molding compound are obtained experimentally. The temperature-dependent CTE of molding compound for Pb-Sn solder and that for lead-free solder are obtained by using strain measurements with well known steel specimen and aluminium specimen as reference specimens, and the CTE's are also measured non-contactly by using moire interferometry. Those results are compared, and the agreement between the two types of strain gage experiment and the moire experiment show the strain gage method used in this paper to be reliable. In the case of the molding compound for Pb-Sn solder, the CTE is measured as approximately $15.8ppm/^{\circ}C$ regardless of the temperature. In the case for the lead-free solder, the CTE is measured as of approximately $9.9ppm/^{\circ}C$ below the temperature of $100^{\circ}C$, and then the CTE is increased sharply depending on the temperature, and reaches to $15.0ppm/^{\circ}C$ at $130^{\circ}C$.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.2
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• pp.31-43
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• 2019

In this study, polymer elastic bumps were fabricated for the flexible electronic package flip chip bonding and the viscoelastic and viscoplastic behavior of the polymer elastic bumps according to the temperature and load were analyzed using FEM and experiments. The polymer elastic bump is easy to deform by the bonding load, and it is confirmed that the bump height flatness problem is easily compensated and the stress concentration on thin chip is reduced remarkably. We also develop a spiral cap type and spoke cap type polymer elastic bump of $200{\mu}m$ diameter to complement Au metal cap crack phenomenon caused by excessive deformation of polymer elastic bump. The proposed polymer elastic bumps could reduce stress of metal wiring during bump deformation compared to metal cap bump, which is completely covered with metal wiring because the metal wiring on these bumps is partially patterned and easily deformable pattern. The spoke cap bump shows the lowest stress concentration in the metal wiring while maintaining the low contact resistance because the contact area between bump and pad was wider than that of the spiral cap bump.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.1
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• pp.29-33
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• 2019

With shrinking form factor and improving performance of electronic packages, high input/output (I/O) density is considered as an important factor. Fan out wafer-level packaging (FO-WLP) has been paid great attention as an alternative. However, FO-WLP is vulnerable to warpage during its manufacturing process. Minimizing warpage is essential for controlling production yield, and in turn, package reliability. While many studies investigated the effect of process and design parameters on warpage using finite element analysis, they did not take uncertainty into consideration. As parameters, including material properties, chip positions, have uncertainty from the point of manufacturing view, the uncertainty should be considered to reduce the gap between the results from the field and the finite element analysis. This paper focuses on the effect of uncertainty of Young's modulus of chip on fan-out wafer level packaging warpage using finite element analysis. It is assumed that Young's modulus of each chip follows the normal distribution. Simulation results show that the uncertainty of Young's modulus affects the maximum von Mises stress. As a result, it is necessary to control the uncertainty of Young's modulus of silicon chip since the maximum von Mises stress is a parameter related to the package reliability.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.1
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• pp.47-56
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• 1999

As the density of logic gates of VLSI chips has rapidly increased, more number of I/O pins has been required. This results in bigger package size and higher packager cost. The package cost is higher than the cost of bare chips for high I/O count VLSI chips. As the density of logic gates increases, the reduction method of the number of I/O pins for a given complexity of logic gates is required. In this paper, we propose the novel I/O interface circuit using CTR (Constant-Transition-Rate) code to reduce 50% of the number of I/O pins. The rising and falling edges of the symbol pulse of CTR codes contain 2-bit digital data, respectively. Since each symbol of the proposed CTR codes contains 4-bit digital data, the symbol rate can be reduced by the factor of 2 compared with the conventional I/O interface circuit. Also, the simultaneous switching noise(SSN) can be reduced because the transition rate is constant and the transition point of the symbols is widely distributed. The channel encoder is implemented only logic circuits and the circuit of the channel decoder is designed using the over-sampling method. The proper operation of the designed I/O interface circuit was verified using. HSPICE simulation with 0.6 m CMOS SPICE parameters. The simulation results indicate that the data transmission rate of the proposed circuit using 0.6 m CMOS technology is more than 200 Mbps/pin. We implemented the proposed circuit using Altera's FPGA and confimed the operation with the data transfer rate of 22.5 Mbps/pin.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.3 s.40
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• pp.1-8
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• 2006

Higher density integration and adoption of new materials in advanced electronic package systems result in severe electrochemical reliability issues in microelectronic packaging due to higher electric field under high temperature and humidity conditions. Under these harsh conditions, metal interconnects respond to applied voltages by electrochemical ionization and conductive filament formation, which leads to short-circuit failure of the electronic package. In this work, in-situ water drop test and evaluation of corrosion characteristics for SnPb solder alloys in D.I. water and NaCl solutions were carried out to understand the fundamental electrochemical migration characteristics and to correlate each other. It was revealed that electrochemical migration behavior of SnPb solder alloys was closely related to the corrosion characteristics, and Pb was primarily ionized in both D.I. water and $Cl^{-}$ solutions. The quality of passive film formed at film surface seems to be critical not only for corrosion resistance but also for ECM resistance of solder alloys.