• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.7-12
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• 2006

Local minority carrier lifetime control by means of particle irradiation is an useful technology for Production of modern silicon Power devices. Crystal damage due to ion irradiation can be easily localized by choosing appropriate irradiation energy and minority tarrier lifetime can be reduced locally only in the damaged layer. In this work, proton irradiation technology was used for improving the switching characteristics of a un diode. The irradiation was carried out with various energy and dose condition. The device was characterized by current-voltage, capacitance-voltage, and reverse recovery time measurements. Forward voltage drop was increased to 1.1 V at forward current of 5 A, which was $120\%$ of its original device. Reverse leakage current was 64 nA at reverse voltage of 100 V, and reverse breakdown voltage was 670 V which was the same voltage as original device without irradiation. The reverse recovery time of device was reduced to about $20\%$ compared to that of original device without irradiation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.1
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• pp.18-22
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• 2006

Epitaxial aluminum nitride films on 6H-SiC (0001) were fabricated using reactive RF magnetron sputtering and post-deposition rapid thermal annealing. The electrical properties of AIN films depending on film thickness and measurement temperature have been observed. Full width at half maximum of AIN (0002) was $0.1204^{\circ}$ (about 430 arcsec) X-ray rocking curve results. The equivalent oxide thickness (EOT) of AIN film was estimated as about 10 nm and the leakage current density was within the order of $10^{-8} 4/cm^2$. The dielectric constant of AIN film estimated from the accumulation region of C-V curve measured at $300^{\circ}C$ was 8.3. The dynamic dielectric constant was obtained as 5.1 from J vs. 1/T plots at the temperature ranging from R.T. to $300^{\circ}C$ From above, estimation temperature dependance of the electrical properties of Al/AIN/SiC MIS devices was affirmed and useful data compilation for the reliabilities of SiC MIS is expected.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.831-837
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• 2002

Scaled SONOS transistors have been fabricated by 0.35$\mu\textrm{m}$ CMOS standard logic process. The thickness of stacked ONO(blocking oxide, memory nitride, tunnel oxide) gate insulators measured by TEM are 2.5 nm, 4.0 nm and 2.4 nm, respectively. The SONOS memories have shown low programming voltages of ${\pm}$8.5 V and long-term retention of 10-year Even after 2 ${\times}$ 10$\^$5/ program/erase cycles, the leakage current of unselected transistor in the erased state was low enough that there was no error in read operation and we could distinguish the programmed state from the erased states precisely The tight distribution of the threshold voltages in the programmed and the erased states could remove complex verifying process caused by over-erase in floating gate flash memory, which is one of the main advantages of the charge-trap type devices. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ cycles can be realized by the programming method for a flash-erased type EEPROM.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.858-864
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• 2002

Aging stabilities of the operating frequency of piezoelectric devices such as filter, oscillator and discriminator are very important. In this study it was studied aging stabilities of the length-extensional vibration mode of Pb(Zr$\^$y/O$_3$+ x[wt%]Cr$_2$Co$_3$ ceramics. PZT ceramics in morphotropic phase boundary have higher aging rates of k$\_$31/ and resonance frequency than those in tetragonal phase or rhombohedral phase. Thermal aging moves the composition with maximum aging rate to Zr-rich side in Cr$_2$O$_3$ not added PZT system. In the PZT system, aging rates of k$\_$31/ and resonance frequency for first 30 days are bigger than those for the following 90 days. Thermal aging decrease those for first 30 days. Aging rate of resonance frequency of the ceramics with x=0.1, y=0.53 and x=0.3, y=0.53 increased by thermal aging.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.54-57
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• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.883-888
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS(micro electro mechanical system) fields because of its application possibility in harsh environments. This paper presents pre-bonding techniques with variation of HF pre-treatment conditions for SiC wafer direct bonding using PECVD(plasma enhanced chemical vapor deposition) oxide. The PECYD oxide was characterized by XPS(X-ray photoelectron spectrometer) and AFM(atomic force microscopy). The characteristics of the bonded sample were measured under different bonding conditions of HF concentration and an applied pressure. The bonding strength was evaluated by the tensile strength method. The bonded interface was analyzed by using SEM(scanning electron microscope). Components existed in the interlayer were analyzed by using FT-IR(fourier transform infrared spectroscopy). The bonding strength was varied with HF pre-treatment conditions before the pre-bonding in the range of 5.3 kgf/cm$^2$to 15.5 kgf/cm$^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.346-349
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• 2002

High Power and high dose ion implantation is essentially needed to make power MOSFET devices based on SiC wafers, because the diffusivities of the impurities such as Al, N, p, B in SiC crystal are very low. In addition, it is needed high temperature annealing for electrical activation of the implanted species. Due to the very high annealing temperature, the surface morphology after electrical activation annealing becomes very rough. We have found the different surface morphologies between implanted and unimplanted region. The unimplanted region showed smoother surface morphology It implies that the damage induced by high energy ion implantation affects the roughening mechanism. Some parts of Si-C bonding are broken in the damaged layer, s\ulcorner the surface migration and sublimation become easy. Therefore the macrostep formation will be promoted. N-type 4H-SiC wafers, which were Al ion implanted at acceleration energy ranged from 30kev to 360kev, were activated at 1600$^{\circ}C$ for 30min. The pre-activation annealing for damage relaxation was performed at 1100-1500$^{\circ}C$ for 30min. The surface morphologies of pre-activation annealed and activation annealed were characterized by atomic force microscopy(AFM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.507-510
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• 2002

In economical points of view, AC loss of high temperature superconducting devices is considered as a serious problem that must be solved. Expecially, in case of HTS cables, HTS tapes are wound helically on the former to reduce AC loss. Critical characteristics of HTS tapes, however, are influenced by mechanical stress as well as electrical, temperature, and magnetical factors. The purpose of this study is to investigate the over current characteristics of HTS tapes given mechanical stress when they are wound on the former. We prepared HTS tapes with the pitch angle 20$^{\circ}$, length 25cm as well as tapes with pitch angle 0$^{\circ}$. When current of over 200A$\_$rms/ was applied, we found out that there are differences to the rate of resistance increase between the case of pitch angle 20$^{\circ}$and that of 0$^{\circ}$. The rate of resistance variation in HTS tapes of pitch angle 20$^{\circ}$increased more slowly than that of pitch angle 0$^{\circ}$. As a result, we concluded that if critical characteristics of HTS tapes are degraded by any external factor, when over current is applied, the current limiting characteristics in HTS tapes won't be able to be expected any more.

• Electrical & Electronic Materials
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• v.8 no.1
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• pp.95-101
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• 1995

Crystallizable glasses with precipitation of celsian, anorthite, wollastonite and gahnite were prepared for the purpose of insulating dielectric layers in devices such as integrated circuit substrates. The starting glasses were prepared by melting the batches for 1 hour at 1450.deg. C and then Quenching to a distilled water. And crystallization behavior of these glasses were studied by DTA, TMA, XRD analysis and by the measurement of dielectric properties. The overall composition of the glass-ceramic consists in weight percent of 30-35% A1$_{2}$O$_{3}$, 13-26% BaO, 5-21% CaO, 10-24% ZnO, 4.5-9.0% TiO$_{2}$ and 4-8% B$_{2}$O$_{3}$. As a result, in barium-rich glasses only celsian phase was developed in the range of 850-900.deg. C. Also, the thermal expansion coefficient, dielectric constant and quality factor of these glass-ceramics were 68*10$^{-7}$ /.deg. C, about 9 and more than 1000, respectively.