• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.67-67
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• 2011

Compound semiconductor/CNTs composites have shown considerably improved efficiency improvement in photovoltaic devices, which is often attributed to two different factors. One is the formation of efficient electronic energy cascade structures. The other effect of CNTs on the performance of photovoltaic devices is the decrement of interfacial resistance. The interfacial resistances at n-type/ p-type materials and/or n-type materials/TCO electrode are reduced by an outstanding electrical property of CNTs. In addition to the effects of CNTs, we report the third reason for increment of efficiency in photovoltaic devices by CNT's well-known electrical field enhancement effects. The improved ${\beta}$ values in reverse-FE currents of CIGS electrode with SWNTs layers indicate the enhancement of electrical field in photovoltaic devices, which implies the acceleration of the electron transfer rate in the cell. Due to the formation of an efficient electronic energy cascade structure and the decrease of the interfacial resistance as well as the improvement of the electrical field in the photovoltaic devices, the power conversion efficiency of electrochemically deposited superstrate-type CIGS solar cells was increased 24.3% in the presence of SWNTs and showed 10.40% conversion efficiency.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제15권12호
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• pp.1021-1026
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• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 한국전기전자재료학회 2006년도 영호남 합동 학술대회 및 춘계학술대회 논문집 센서 박막 기술교육
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• pp.149-151
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• 2006

The surface properties of electrical devices studied by fractal phenomenon were investigated. The SEM photographs of devices surface were changed by binary code and it were analyzed by fractal dimension. The void of devices surface was found by fractal program. The relation between grain density and electrical properties are able to expect to fractal dimension. The grain size in varistors surface was decreased by increasing of oxide antimony addition. The fractal dimension and electrical properties of devices surface was related to between grain boundary and grain density. The grain size was decreased by increasing of fractal dimensions.

• Journal of electromagnetic engineering and science
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• 제7권1호
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• pp.12-16
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• 2007

A UHF band wireless identification system based on passive surface acoustic wave(SAW) devices is presented in this paper. SAW ID tags were fabricated on Y-Z $LiNbO_3$ piezoelectric substrate with a good electro-mechanical coupling property. To reduce degradation of the antenna performance associated with the piezoelectric materials, an efficient design of the SAW RFID antenna is introduced. By measuring the parameters of the SAW ID tag, the performance of the antenna was tested by experimentation.

• Journal of Institute of Control, Robotics and Systems
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• 제7권10호
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• pp.837-842
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• 2001

In this paper, we design and implement the DC characteristic measurement system for semiconductor devices. The proposed system is composed of 4 SMU(Source and Measure Unit) channels. Various efforts in hardware and software have been made to reduce the measurement errors. Internal and external sources of errors in measurement system especially in pA range measurement have been identified and removed. Also, various digital signal processing techniques are developed. Calibration is executed under the control of microprocessor periodically. Experimental results show that the implemented system can measure the DC characteristic of semiconductor devices with less than 0.2% error in various voltage and current source/measurement range.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• Applied Science and Convergence Technology
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• 제23권6호
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• pp.317-327
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• 2014

In order to develop nano-devices with much lower power consumption for beyond-CMOS applications, the fundamental understanding and precise control of the electronic properties of ultrathin transition metal oxide (TMO) films are strongly required. The metal-insulator transition (MIT) is not only an important issue in solid state physics, but also a useful phenomenon for device applications like switching or memory devices. For potential use in such application, the electronic structures of MIT, observed for TMO nano-structures, have been investigated using a synchrotron radiation angle-resolved photoelectron spectroscopy system combined with a laser molecular beam epitaxy chamber and a scanning photoelectron microscopy system with 70 nm spatial resolution. In this review article, electronic structures revealed by soft X-ray nano-spectroscopy are presented for i) polarity-dependent MIT and thickness-dependent MIT of TMO ultrathin films of $LaAlO_3/SrTiO_3$ and $SrVO_3/SrTiO_3$, respectively, and ii) electric field-induced MIT of TMO nano-structures showing resistance switching behaviors due to interfacial redox reactions and/or filamentary path formation. These electronic structures have been successfully correlated with the electrical properties of nano-structured films and nano-devices.

• Proceedings of the Korean Vacuum Society Conference
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.90-90
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• 2012

The electron/hole injections in organic electronic devices have long been an issue due to the large energy level mismatches between electrode and organic layer. To utilize the organic materials in electronic devices, functional thin layers have been used, which reduce the electron/hole injection barrier from electrode to organic material. Typically, inorganic compounds and organic molecules are used as an electron and hole injection layer, respectively. Recently, CsN3 and 1,4,5,8,- naphthalene-tetracarboxylic-dianhydride (NTCDA) are reported as a potential electron and hole injection layers. CsN3 shows unique properties that it breaks into Cs and N and thus Cs can dope organic layer into n-type. On the other side, hole injection anode, NTCDA forms gap states with anode material. In this presentation, we show the electronic structure changes upon the insertion of CsN3 and NTCDA at proper interfaces to reduce the charge injection barriers. These barrier reductions are correlated with device characteristics.

• Journal of Magnetics
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• 제22권1호
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• pp.109-121
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• 2017

Ferrofluids are a special category of smart nanomaterials which shows normal liquid behavior coupled with superparamagnetic properties. One of the earliest and most prospective applications of ferrofluids is in damping, which has prominent advantages compared with conventional damping devices: simplicity, flexibility and reliability. This paper presents the basic principles that play a major role in the design of ferrofluid damping devices. The characteristics of typical ferrofluid damping devices including dampers, vibration isolators, and dynamic vibration absorbers are compared and summarized, and then recent progress of vibration energy harvesters based on ferrofluid is briefly described. Additionally, we proposed a novel ferrofluid dynamic vibration absorber in this paper, and its damping efficiency was verified with experiments. In the end, the critical problems and research directions of the ferrofluid damping technology in the future are raised.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제19권6호
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• pp.586-590
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• 2006

This paper deals with the application of a partial discharge (PD) test on low-voltage electrical and electronic devices, which is recently being accepted as a non-destructive and a effective dielectric test method. A comparative analysis combined with the Withstand Voltage Test (WVT) specified in IEC standards was carried out on low-voltage insulation transformers. The results showed that the WVT causes insulation degradation of the specimen during the test by applying high voltage. However, the PD test can be performed in ranges from 30 % to 50 % of the test voltage specified in the WVT. Therefore, the PD test is successfully applicable for a non-destructive test method on low-voltage electrical and electronic devices as a replacement of the WVT.