• 제목/요약/키워드: Electronic device

검색결과 4,544건 처리시간 0.028초

표면 Texturization을 가진 Photovoltaic Device 내부의 열 분포 특성에 관한 연구 (A Study of the Thermal Characteristics of a Photovoltaic Device with Surface Texturization)

  • 정지철;문경숙;구상모
    • 한국전기전자재료학회논문지
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    • 제23권7호
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    • pp.509-512
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    • 2010
  • The thermal distribution of 2D and 3D p-n photovoltaic diode structures with and without surface texturing has been studied. By analysis of the numerical simulation results of the I-V characteristics and lattice temperature distributions the effect of different texturing structures on the characteristics of silicon p-n photovoltaic devices has been studied systematically. The efficiency of the device having surface texturing shows more than ~2% enhancement compared to the reference devices which did not have texturing. In addition, the effect of the density of the texturing groove has been studied and it has been confirmed that the texturing structure not only improves the light trapping but also plays an important role in the heat radiation.

DC 및 AC 스트레스에서 Lateral DMOS 트랜지스터의 소자열화 (Hot-Carrier-Induced Degradation of Lateral DMOS Transistors under DC and AC Stress)

  • 이인경;윤세레나;유종근;박종태
    • 대한전자공학회논문지SD
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    • 제44권2호
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    • pp.13-18
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    • 2007
  • 본 연구에서는 Lateral DMOS 소자열화 메카니즘이 게이트 산화층의 두께에 따라 다른 것을 측정을 통하여 알 수 있었다. 얇은 산화층 소자는 채널에 생성되는 계면상태와 drift 영역에 포획되는 홀에 의하여 소자가 열화 되고 두꺼운 산화층 소자에서는 채널 영역의 계면상태 생성에 의해서 소자가 열화 되는 것으로 알 수 있었다. 그리고 소자 시뮬레이션을 통하여 다른 열화 메카니즘을 입증할 수 있었다. DC 스트레스에서의 소자 열화와 AC 스트레스에서 소자열화의 비교로부터 AC스트레스에서 소자열화가 적게 되었으며 게이트 펄스의 주파수가 증가할수록 소자열화가 심함을 알 수 있었다. 그 결과로부터 RF LDMOS 에서는 소자열화가 소자설계 및 회로설계에 중요한 변수로 작용할 수 있음을 알 수 있었다.

LB법에 의한 분자소자의 기초연구 (I) (A Basic Study on Molecular Electronic Device by Langmuir-Blodgett Technique)

  • 권영수
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1989년도 추계학술대회 논문집 학회본부
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    • pp.98-100
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    • 1989
  • Langmuir-Blodgett(LB) technique will be used to produce ultra thin film, and then characterization of the physical and electrical properties of LB ultra thin films, this study will be an investigation for the possibilities of the ultra thin films as an Molecular Electronic Device.

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ZnO-나노와이어/PVDF 복합체를 압전 활성층으로 한 나노발전기 소자 (Nanogenerator Device Based on Piezoelectric Active Layer of ZnO-Nanowires/PVDF Composite)

  • 임영택;신백균
    • 한국전기전자재료학회논문지
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    • 제27권11호
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    • pp.740-745
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    • 2014
  • ZnO nanowires were grown by hydrothermal synthesis process and piezoelectric poly vinylidene fluoride (PVDF) was then coated on top of the ZnO-nanowires by spray-coating technique. The composite layer of ZnO-nanowires/PVDF was applied to an energy harvesting device based on piezoelectric-conversion mechanism. A defined mechanical force was given to the nanogenerator device to evaluate their electric power generation characteristics, where output current density and voltage were examined. Electric power generation property of the ZnO-nanowires/PVDF based nanogenerator device was compared to that of the nanogenerator device with ZnO-nanowires as single active layer. Effect of the ZnO-nanowires on improvement of power generation was discussed to examine its feasibility for the nanogenerator device.

Interference Mitigation Scheme for Device-to-Device MIMO Communications Underlaying a Cellular Network

  • Nam, Yujin;So, Jaewoo;Kim, Jinsung
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제11권4호
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    • pp.1841-1865
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    • 2017
  • This paper proposes a new interference mitigation scheme for device-to-device (D2D) communications underlaying a cellular network. The object of the proposed scheme is to determine the number of data streams, a precoding matrix, and a decoding matrix of D2D networks so as to maximize the system capacity given the number of data streams of a cellular network while satisfying the constraint of the inter-system interference from D2D networks to the cellular network. Unlike existing interference mitigation schemes based on the interference alignment technique, the proposed scheme operates properly regardless of the number of data streams of a cellular network and moreover it does not require changing the precoding and decoding matrices of a cellular network. The simulation results demonstrate that the proposed scheme significantly increases the system capacity by mitigating the intra- and inter-system interference.

프로그램 가능한 논리 회로 구성을 위한 PIP 앤티퓨즈의 전기적 특성 (Electrical Characteristics of the PIP Antifuse for Configuration of the Programmable Logic Circuit)

  • 김필중;윤중현;김종빈
    • 한국전기전자재료학회논문지
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    • 제14권12호
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    • pp.953-958
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    • 2001
  • The antifuse is a semi-permanent memory device like a ROM which shows the open or short state, and a switch device connecting logic blocks selectively in FPGA. In addition, the antifuse has been used as a logic device to troubleshoot defective memory cells arising from SDRAM processing. In this study, we have fabricated ONO antifuses consisted of PIP structure. The antifuse shows a high resistance more than several G Ω in the normal state, and shows a low resistance less than 500 Ω after program. The program resistance variation according to temperature shows the very stable value of $\pm$20 Ω. At this time, its program voltage shows 6.7∼7.2 V and the program is performed within 1 second. Therefore this result shows that the PIP antifuse is a very stable and programmable logic device.

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n-MOSFET 정전기 방전 분석 (Electrostatic Discharge Analysis of n-MOSFET)

  • 차영호;권태하;최혁환
    • 한국전기전자재료학회논문지
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    • 제11권8호
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    • pp.587-595
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    • 1998
  • Transient thermal analysis simulations are carried out using a modeling program to understand the human body model HBM ESD. The devices were simulated a one-dimensional device subjected to ESD stress by solving Poison's equation, the continuity equation, and heat flow equation. A ramp rise with peak ESD voltage during rise time is applied to the device under test and then discharged exponentially through the device. LDD and NMOS structures were studied to evaluate ESD performance, snap back voltages, device heating. Junction heating results in the necessity for increased electron concentration in the space charge region to carry the current by the ESD HBM circuit. The doping profile adihacent to junction determines the amount of charge density and magnitude of the electric field, potential drop, and device heating. Shallow slopes of LDD tend to collect the negative charge and higher potential drops and device heating.

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문자구동형 후막 전계발광소자 제작 및 구동회로 설계 (Driving Circuit Design and Manufacture of Powder Electroluminescent Device for Information Display)

  • 이종찬;조황신;성현호;박응규;박대희
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 하계학술대회 논문집 C
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    • pp.1730-1732
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    • 2000
  • Powder Electroluminescent Device is the solid state device which has a low power consumption, large area emission with uniformity, easy manufacturing, simple structure, and flexible mechanically. In this paper, we made the information display with the powder electroluminescent device using back-light and designed the driving circuit.

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