• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.22-28
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• 2009

As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.6
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• pp.1145-1152
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• 2019

In this paper, a low power current mode 12-bit ADC(: Analog to Digital Converter) is proposed to mix digital circuits and analog circuits with the advantages of low power consumption and high speed operation. The proposed 12 bit ADC is implemented by using 4-bit ADC in a cascade structure, so its power consumption can be reduced, and the chip area can be reduced by using a conversion current mirror circuit. The proposed 12-bit ADC is SK Hynix 350nm process, and post-layout simulation is performed using Cadence MMSIM. It operates at a supply voltage of 3.3V and the area of the proposed circuit is 318㎛ x 514㎛. In addition, the ADC shows the possibility of operating with low power consumption of 3.4mW average power consumption in this paper.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.561-564
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• 2004

The motion estimation which requires huge computation consumes large power in a video encoder. Although a number of fast-search algorithms are proposed to reduce the power consumption, the smaller the computation, the worse the performance they have. In this paper, we propose an architecture that a low energy management scheme can be applied with several fast-search algorithm. In addition. we show that ECVH, a software scheduling scheme which dynamically changes the search algorithm, the operating frequency, and the supply voltage using the remaining slack time within given power-budget, can be applied to the architecture, and show that the power consumption can be reduced.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.131-144
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• 2015

An extensive investigation of the influence of gate engineering on the CNTFET switching, high frequency and circuit level performance has been carried out. At device level, the effects of gate engineering on the switching and high frequency characteristics for CNTFET have been theoretically investigated by using a quantum kinetic model. It is revealed that hetero - material - gate CNTFET(HMG - CNTFET) structure can significantly reduce leakage current, enhance control ability of the gate on channel, and is more suitable for use in low power and high frequency circuits. At circuit level, using the HSPICE with look - up table(LUT) based Verilog - A models, the performance parameters of circuits have been calculated and the optimum combinations of ${\Phi}_{M1}/{\Phi}_{M2}/{\Phi}_{M3}$ have been concluded in terms of power consumption, average delay, stability, energy consumption and power - delay product(PDP). We show that, compared to a traditional CNTFET - based circuit, the one based on HMG - CNTFET has a significantly better performance (SNM, energy, PDP). In addition, results also illustrate that HMG - CNTFET circuits have a consistent trend in delay, power, and PDP with respect to the transistor size, indicating that gate engineering of CNTFETs is a promising technology. Our results may be useful for designing and optimizing CNTFET devices and circuits.

• ETRI Journal
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• v.37 no.1
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• pp.118-127
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• 2015

The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.351-354
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• 2000

In the past, we proposed an IDDQ testable design method for static CMOS PLA circuits. All bridging faults can be detected in NOR planes of our testable designed PLA circuits by IDDQ testing with 4 kinds of test input vectors which are independent of the logical functions to be realized. However, the testable designed PLA circuits consume large power in the normal operation. In this paper, a new IDDQ testable design method is proposed and evaluated by some experiments. The experimental results show that the PLA circuit designed with our method can work with low power consumption than the previous one.

• 한국태양에너지학회:학술대회논문집
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• 2008.11a
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• pp.126-131
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• 2008

The large buildings in Korea usually use the generators to control the peak load of electronic consumption during the summer. It is necessary that these generators emit carbon dioxide, since they use gas or gasoline for their fuel. This study is to analyze the data of electronic consumption and operation of the generators at COEX, one of the representative complex building clusters in Korea, and to compare to the amount of carbon dioxide emitted per 1kWh from the domestic power plant by analogizing the frequency of using the generator during the summer and the amount of fuel consumption by the capacity of the generator and estimating the amount of carbon dioxide emitted from the generator.

• Journal of the Institute of Convergence Signal Processing
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• v.16 no.3
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• pp.115-121
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• 2015

A device which could cut off the consumption of standby power by electric or electronic devices at homes and offices while waiting for a command to carry out the main functions from the inside or the outside was developed at a low price. Efforts to save standby power have been made on a global scale as well as by advanced countries. The consumption of standby power in South Korea is also increasing gradually due to increasing trend in the number of electronic and electric devices per household, becoming a major factor for waste of electric energy. The previous standby power cutoff devices themselves have high electric energy consumption and complicated structures, making the purpose less meaningful. Therefore, a low-priced standby power cutoff device is suggested in this study, which compensates such problems and cuts off the consumption of standby power completely. The circuit of the suggested standby power cutoff device was designed and implemented by applying it to an earth leakage breaker and an (electrical) outlet. Experimental results show its superiority.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.8
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• pp.985-994
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• 2012

This paper presents the real channel measurements and investigates their statistical characterization in wireless body area network(WBAN). In on-/off body channel, the measurements are performed with some representative human movements for considering human movements. Moreover, three signal transmission schemes with outage constraint are studied for getting total power consumption in each transmission scheme. Using the real channel measurements, between theoretical and realistic simulation are compared. This paper shows that power efficiency is improved through cooperative communication, and how much position of sensor node and human movement affect signal transmission power.

• Journal of Power System Engineering
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• v.21 no.4
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• pp.84-93
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• 2017

This study was carried out to improve the electric power consumption of HVAC in the blow mold machine(BMM) and work environment. The experiment was conducted with the simulated HVAC system of 1/15 of the actual BMM. The temperature of main facility and two preheaters was fixed at 200 and $60^{\circ}C$ respectively in all test conditions. The measured points of temperature were chosen as critical locations considering the work environment. The tendency of temperature distributions decreases as the duct was closed to the main facility. The reduction rate of power consumption of HVAC increases up to 32.3% when both duct and cooling systems are operated. Also the efficiency of HVAC is improved about 9% through the modified design of duct system. It notes that the electric power consumption of HVAC can be reduced by the optimum design and operating condition of duct and cooling system.