• Journal of Power Electronics
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• v.16 no.6
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• pp.2035-2044
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• 2016

In order to match the voltages between high voltage battery stacks and low voltage super-capacitors with a high conversion efficiency in hybrid energy sources electric vehicles (HESEVs), a high ratio bidirectional DC-DC converter with a synchronous rectification H-Bridge is proposed in this paper. The principles of high ratio step-down and step-up operations are analyzed. In terms of the bidirectional characteristic of the H-Bridge, the bidirectional synchronous rectification (SR) operation is presented without any extra hardware. Then the SR power switches can achieve zero voltage switching (ZVS) turn-on and turn-off during dead time, and the power conversion efficiency is improved compared to that of the diode rectification (DR) operation, as well as the utilization of power switches. Experimental results show that the proposed converter can operate bidirectionally in the wide ratio range of 3~10, when the low voltage continuously varies between 15V and 50V. The maximum efficiencies are 94.1% in the Buck mode, and 93.6% in the Boost mode. In addition, the corresponding largest efficiency variations between SR and DR operations are 4.8% and 3.4%. This converter is suitable for use as a power interface between the battery stacks and super-capacitors in HESEVs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.8
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• pp.29-35
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• 2010

In this paper we propose a new pattern generator for a BIST architecture that can reduce the power consumption during test application. The principle of the proposed method is to reconstruct an LFSR circuit to reduce WSAs of the heavy nodes by suppressing the heavy inputs. We propose algorithms for finding heavy nodes and heavy inputs. Using the Modified LFSR which consists of some AND/OR gates trees and an original LFSR, BIST applies modified test patterns to the circuit under test. The proposed BIST architecture with small hardware overhead effectively reduces the average power consumption during test application while achieving high fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 30.5%.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.37-43
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• 2008

The performance and hardware complexity of LDPC decoders depend on the design parameters of quantization, the clipping threshold $c_{th}$ and the number of quantization bits q, and also on the maximum number of decoding iterations. In this paper, the BER performances of LDPC codes are evaluated according to the clipping threshold $c_{th}$ and the number of quantization bits q through the simulation studies. By comparing the quantized Min-Sum algorithm with the ideal Min-Sum algorithm, it is shown that the quantized case with $c_{th}=2.5$ and q=6 has the best performance, which approaches the idea case. The decoding complexities are calculated and the word error rates(WER) are estimated by using the pdf which is obtained through the statistical analyses on the iteration numbers. These results can be utilized to tradeoff between the decoding performance and the complexity in LDPC decoder design.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.681-687
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• 2014

Nuclear industries have faced unfavorable circumstances such as an obsolescence of the instrumentation and control system, and therefore nuclear society is striving to resolve this issue fundamentally. IEC and IAEA judge that FPGA technology is a good replacement for Programmable Logic Controller (PLC) of Nuclear Instrumentation and Control System. FPGAs are currently highlighted as an alternative means for obsolete control systems. Because the main function inside an FPGA is initially developed as software, good software quality can impact the reliability of an FPGA-based controller. Therefore, it is necessary to establish a software development aspect strategy that enhances the reliability of an FPGA-based controller. In terms of software development, HDL-Programmed Device (HPD) Development Life Cycle is applied into FPGA-based Controller. The burn-in test and environmental(temperature) test should be performed in order to apply into nuclear instrumentation and control system. Therefore it is ensured that the developed FPGA-based controller are normally operated for 352 hours and 92 hours in test chamber of Korea Institute of Machinery and Materials (KIMM).

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.6
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• pp.673-679
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• 2014

The important requirements of designing a pattern classifier are high throughput and low memory requirements, and low cost hardware implementation. A pattern classifier by using Multiple Attractor Cellular Automata(MACA) proposed by Maji et al. reduced the complexity of the classification algorithm from $O(n^3)$ to O(n) by using Dependency Vector(DV) and Dependency String(DS). In this paper, we generate a pattern classifier using LFSR to improve efficiently the space and time complexity and we propose a method for finding DV by using the 0-basic path. Also we investigate DV and the attractor of the generated pattern classifier. We can divide an n-bit DS by m number of $DV_i$ s and generate various pattern classifiers.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.2
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• pp.325-330
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• 2017

Face recognition technology has been studied for decades and is being used in various areas such as security, entertainment, and mobile services. The main problem with face recognition technology is that the recognition rate is significantly reduced depending on the environmental factors such as brightness, illumination angle, and image rotation. Therefore, in this paper, we propose a robust face recognition against lighting variation using CNN which has been recently re-evaluated with the development of computer hardware and algorithms capable of processing a large amount of computation. For performance verification, PCA, LBP, and DCT algorithms were compared with the conventional face recognition algorithms. The recognition was improved by 9.82%, 11.6%, and 4.54%, respectively. Also, the recognition improvement of 5.24% was recorded in the comparison of the face recognition research result using the existing neural network, and the final recognition rate was 99.25%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1725-1730
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• 2017

The acceleration sensor and the gyroscopic sensor are used as representative sensors to detect repetitive motion and have been used to analyze various sporting components. However, both sensors have problems with noise sensitivity and accumulation of errors. There have been attempts to use two sensors together to overcome hardware problems. The complementary filter has shown successful results in mitigating the problems of both sensors by minimizing the disadvantages of accelerometer and gyroscope sensors and maximizing their advantages. In this paper, we proposed a modified method using neural network to reduce variable. The neural network is an algorithm that can precisely measure even in unexpected environments or situations by pre-learning the number of various cases. The proposed method applies a Neural Network by dividing the repetitive motion into three sections, the first, the middle and the end. As a result, the recognition rate is 96.35%, 98.77%, 96.92% and the accuracy is 97.18%.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.219-225
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• 2014

The purpose of this paper is to control of the low-speed, high-precision PMSM 2-axes pitch/turning. In this paper, apply the PAM-PWM inverter for it. However, The PAM-PWM inverter, control algorithms and hardware is complex. But it is possible to improve the performance in the low-speed operation can reduce the effect of the PWM ripple and Dead Time of inverter by applying suitable DC-bus voltage control. The direct driver PMSM(Permanent Magnet Synchronous Motor) configured to vector control part, PAM control part and the other controller. The vector control part includes PI current, speed control, additional space vector modulation. PAM control part has to have PI voltage controller and P current controller for DC-bus voltage control. Besides, the motor position estimator, the speed estimator and the counter electromotive force and Dead Time Compensation are added. With this arrangement, PMSM was driven with a low pole pitch/turning by performing the current control to the current command or torque command is the paper. As a result, it was possible to minimize the disturbance component that appears in the drive in proportion to the DC voltage magnitude. The use of a hydraulic drive method for a two-axis bubble column is a typical tank. When using the PWM PAM inverter driver is in the turret can be driven by high-precision, low vibration, low noise compared to the hydraulic drive may contribute to the computerization of the turret.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.12
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• pp.1329-1336
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• 2015

Due to the advances in hardware technologies for low-power CMOS cameras, there have been various researches on wireless video sensor network(WVSN) applications including agricultural monitoring and environmental tracking. In such a system, its core technologies include video compression and wireless transmission. Since data of video sensors are bigger than those of other sensors, it is particularly necessary to estimate precisely the traffic after video encoding. In this paper, we present an estimation method for the encoded video traffic in WVSN networks. To estimate traffic characteristics accurately, the proposed method first measures complexities of frames and then applies them to the bit rate estimation adaptively. It is shown by experimental results that the proposed method improves the estimation of bit rate characteristics by more than 12% as compared to the existing method.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.6
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• pp.1337-1342
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• 2012

In recent years, many researches in Home Networking are being progressed actively. Most of techniques for Home Networking are based on wired but the technique for wireless connection is also needed. This paper focuses on wireless connection in Home Networking. Of many of wireless technologies, such as Wireless LAN, Bluetooth, or HomeRF, we especially propose to apply the new technique called Wireless Sensor Network. We present hardware and protocol stack design consideration for wireless sensor node and wireless sensor network, and then we present how to apply wireless sensor network to Home Networking and how to constitute Wireless Home-Networking with a variety of sensor nodes. Finally, we introduce the wireless sensor node system designed by us and conclude this paper.