• The Transactions of the Korean Institute of Power Electronics
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• v.23 no.2
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• pp.121-128
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• 2018

This work proposes a simple control method of a buck-type active power decoupling circuit that can minimize the ripple values in the dc link voltage. The proposed method utilizes a simplified duty calculation method and an optimal compensation gain tracking algorithm with variable-step approach. Thus, the dc link voltage ripple can be effectively reduced through the proposed method along with rapid response in tracking the optimum compensation gain. Moreover, the proposed method has better dynamic responses in the load fluctuation or abnormal situation. MATLAB/Simulink simulation and hardware-in-the-loop-simulation(HILS)-based experimental results are presented to validate the effectiveness of the proposed control method.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.643-644
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• 2006

In this paper, WiBro system which is one of the mobile wireless metropolitan area network systems is presented. WiBro is an OFDMA system which has a sub-channelization process unlike conventional OFDM systems. The sub-channelization is the time consuming processing, so a time-efficient hardware architecture is needed. WiBro RAS(Radio Access Station) demodulator is designed with Verilog HDL, and the gate count is 81k using the $0.18{\mu}m$ processing.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.649-650
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• 2006

An analysis is made of a new 1Gbps MB-OFDM system having same bandwidth and transmission power as conventional 480Mbps system. $2{\times}2$ MIMO scheme and MLD with soft decision demodulation algorithm are proposed in this paper. As a result of hardware implementation, it showed as same performance as conventional MB-OFDM system, while presenting doubled data rates and low complexity.

• Proceedings of the KIEE Conference
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• 1995.07b
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• pp.738-741
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• 1995

This disseration realized the simple digital controller board using ${\mu}$-PD 70320 microprocessor has characteristics that are low cost, simple hardware organization, convenient and interchangeable with the 8086 for the servo system. We gave the control algorithm such as PD control. Self tuning adaptive control and Fuzzy control to the realized controller board and made a new real number data type for a high accuracy control. Users can select of suitable for the control algorithim. In the result of simulation and experiment shown a good performance.

• ETRI Journal
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• v.37 no.4
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2103-2105
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• 2003

본 논문에서는 주변의 잡음에 의해 통신 환경이 나쁜 시스템에서 통신의 안정성과 고속성과 원거리 통신의 구현을 중점으로 연구하였다. 전동차와 같이 Serial Communication을 이용해 차량사이 통신을 하는 경우 주변의 고전압, 고전류의 잡음에 의해 통신 Packet이 파손될 수 있으며 심지어 통신 모듈이 파괴되는 현상도 발생한다. 이를 위해 펄스트랜스 포머를 사용해 Hardware의 보호 뿐아니라 고속의 안정적인 통신을 구현 할 수 있다. 이는 펄스트랜스 포머의 특성상 하드웨어적으로 분리된 통신선과 통신모듈로 인한 안전성과 원거리 통신을 실현 하였으며 동기통신을 통한 빠른 속도와 FM0, FM1, Manchester 부호 방식에 의한 빠르고 안정한 통신을 제공하기 때문이다.

• Journal of information and communication convergence engineering
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• v.19 no.3
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• pp.175-179
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• 2021

Enhancing the reliability of the system is important for recent system-on-chip (SoC) designs. This importance has led to studies on fault diagnosis and tolerance. Fault-injection (FI) techniques are widely used to measure the fault-tolerance capabilities of resilient systems. FI techniques suffer from limitations in relation to environmental conditions and system features. Moreover, a hardware-based FI can cause permanent damage to the target system, because the actual circuit cannot be restored. Accordingly, we propose a simulation-based FI framework based on the Verilog Procedural Interface for measuring the failure rates of SoCs caused by soft errors. We execute five benchmark programs using an ARM Cortex M0 processor and inject soft errors using the proposed framework. The experiment has a 95% confidence level with a ±2.53% error, and confirms the reliability and feasibility of using proposed framework for fault analysis in SoCs.

• Journal of Sensor Science and Technology
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• v.30 no.5
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• pp.286-289
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• 2021

Image classification is one of the fundamental applications of computer vision. It enables a system to identify an object in an image. Recently, image classification applications have broadened their scope from computer applications to edge devices. The convolutional neural network (CNN) is the main class of deep learning neural networks that are widely used in computer tasks, and it delivers high accuracy. However, CNN algorithms use a large number of parameters and incur high computational costs, which hinder their implementation in edge hardware devices. To address this issue, this paper proposes a lightweight image classifier that provides good accuracy while using fewer parameters. The proposed image classifier diverts the input into three paths and utilizes different scales of receptive fields to extract more feature maps while using fewer parameters at the time of training. This results in the development of a model of small size. This model is tested on the CIFAR-10 dataset and achieves an accuracy of 90% using .26M parameters. This is better than the state-of-the-art models, and it can be implemented on edge devices.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.414-415
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• 2019

본 논문은 HVDC(High Voltage Direct Current)에 적용된 MMC(Modular Multilevel Converter)의 제어 알고리즘 개발을 위한 HILS(Hardware In the Loop Simulation)을 위한 모델링 및 HILS 시스템 구축 예를 보인다. 전력 계통, MMC, 풍력 발전 등의 HILS 적용 MATLAB/SIMULINK 모델 및 FPGA(Field Programmable Gate Array)를 이용한 제어기 개발 내용을 보인다. 시뮬레이션 모델과 FPGA 제어기를 이용하여 구축한 OPAL-RT 기반의 실험 결과를 보인다.