• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.57-64
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• 2008

This paper proposes a new test data compression scheme which has good performance. The proposed scheme is composed of adding transition stage and shifting transition stage using don't care remapping technique. The experimental results show that the new scheme provides higher compression ratio than RL-huffman encoding which is the one of the highest performance schemes, and requires smaller hardware overhead. Therefore it can be widely used as a practical solution for test data compression.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.9
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• pp.531-538
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• 2005

This paper proposes an expert system which is able to enhance the accuracy and productivity by determining the test strategy based on heuristic rules for test of the hybrid electronic circuit board producted massively in production line. The test heuristic rules are obtained from test system designer, test experts and experimental results. The guarding method separating the tested device with circumference circuit of the device is adopted to enhance the accuracy of measurements in the test of analog devices. This guarding method can reduce the error occurring due to the voltage drop in both the signal input line and the measuring line by utilizing heuristic rules considering the device impedance and the parallel impedance. Also, PSA(Parallel Signature Analysis) technique Is applied for test of the digital devices and circuits. In the PSA technique, the real-time test of the high integrated device is possible by minimizing the test time forcing n bit output stream from the tested device to LFSR continuously. It is implemented in Visual C++ computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. Finally, the effectiveness of the builded expert system is proved by simulating the several faults occurring in the mounting process the electronic devices to the surface of PCB for a typical hybrid electronic board and by identifying the results.

• Smart Media Journal
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• v.2 no.1
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• pp.17-26
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• 2013

Electronic bulletin boards, has been used as an effective tool in various information delivery. However, many electronic bulletin board as a one-way information passed by the interactivity is lacking. In this paper, the interaction of the information, while maintaining an electronic bulletin board that can be operated on a variety of platforms, the Android-based software and hardware for the design and implementation. The interaction of users of electronic bulletin boards, and information can be naturally-type content support Android framework was designed to allow Android APP. Android APP using the administrator also was designed automatic installation and FORUMS so that you can run. Naturally gather information, and all the people that interact through bulletin boards, so you can take advantage.

• Journal of the Korea Institute of Military Science and Technology
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• v.22 no.2
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• pp.170-178
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• 2019

Classification of radar signals in the field of electronic warfare is a problem of discriminating threat types by analyzing enemy threat radar signals such as aircraft, radar, and missile received through electronic warfare equipment. Recent radar systems have adopted a variety of modulation schemes that are different from those used in conventional systems, and are often difficult to analyze using existing algorithms. Also, it is necessary to design a robust algorithm for the signal received in the real environment due to the environmental influence and the measurement error due to the characteristics of the hardware. In this paper, we propose a radar signal classification method which are not affected by radar signal modulation methods and noise generation by using deep learning techniques.

• Transactions of the Korean Society of Automotive Engineers
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• v.10 no.1
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• pp.195-202
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• 2002

By using modeling and simulation. today's design engineers are simultaneously reducing time to market and decreasing the cost of development, while increasing the quality and reliability of their products. A driving simulator is the best example of this method and allows virtual designs of control systems, electronic systems, mechanical systems and hydraulic system of a vehicle to be evaluated before costly prototyping. The objective of this Paper is to develop the virtual Proving: ground using a driving simulator and to show its capabilities of an automotive system development tool. For this purpose, including a real-time vehicle dynamics analysis system, the PC-based driving simulator and the virtual proving ground are developed by using VR(Virtual Reality) techniques. Also ABS HIL(Hardware-In-the-Loop ) simulation is performed successfully.

• The Transactions of the Korea Information Processing Society
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• v.2 no.1
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• pp.106-118
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• 1995

In this work, the optimized design methodology in high-level synthesis related with scheduling and hardware allocation is developed by simulated annealing technique effectively modified . Applying this method to digital filter design, the optimized tradeoff problem of speed and hardware costs in pipelined digital filter case and array digital filter case are investigated. While, it is confirmed that the suggested method gives the improved cost function value faster and can be used in complicated digital filter design.

• Journal of Electrical Engineering and Technology
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• v.2 no.4
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• pp.500-504
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• 2007

In this paper, the induction motor rotor fault diagnosis system using current signals, which are measured using axis-transformation method, and speed, which is estimated using current information, are presented. In inverter-fed motor drives unlike line-driven motor drives the stator currents have numerous harmonics components and therefore fault diagnosis using stator currents is very difficult. The current and speed signal for rotor fault diagnosis needs to be precise. Also, high resolution information, which means the diagnosis system, demands additional hardware such as low pass filter, high resolution ADC, encoder and etc. Therefore, the proposed axis-transformation and speed estimation method are expected to contribute to low cost fault diagnosis systems in inverter-fed motor drives without the need for an encoder and any additional hardware. In order to confirm validity of the developed algorithms, various experiments for rotor faults are tested and the line current spectrum of each faulty situation using Park transformation and speed estimation method are compared with the results obtained from fast Fourier transforms.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.4
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• pp.26-36
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• 2000

This paper proposes a neural network algorithm for real-time multiprocessor scheduling problem. The proposed algorithm is developed base on Hopfield neural network for a benefit of parallel processing, in order to finish a requested task within a deadline time. To compare the performance of the proposed algorithm, we used EDA and LLA algorithm that has studied real-time multiprocessor scheduling before. The proposed algorithm is implemented hardware using VHDL.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.297-300
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• 2002

In this study, we implement the potable blood gas analyzer measuring pH, pCO$_2$and pCO$_2$of the arterial blood. The implemented system by this study is divided into hardware and software part and also the hardware portion is parted by mechanism and electronic circuit unit. The system program is composed of operating, washing, correcting and measuring program. And to correct the system, two-point calibration method is used, one-point calibration method is also added for more accuracy, and system program is coded. For verifying the implemented system, We examine to response property of each electrode. And evaluate accuracy of the system using standard reagent and was construed as statistical.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.60-66
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• 2000

This paper proposes a design of phone card IC with the self-test features and the hardware and software security functions. We design and verify the proposed functions with modeling the terminal system environment. The proposed phone card IC provides instructions and a non-volatile memory block containing the manufacturer / issuer / user information, the unit (money) value, and the security key. The self-test functions are designed to improve the test time degradation due to a serial I/O communication. Also some security features are implemented using hardware and software approaches.