• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.2
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• pp.74-80
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• 2008

Spatio-temporal filters are capable of reducing noise from moving pictures, which cannot be dealt with by spatial filters. However, the algorithm is too complicated to be realized as hardware. We implemented a real-time spatio-temporal noise reduction system, using at most three frames, based upon adaptive mean filter algorithm. Some factors which interfere with hardware implementation were modified. Noise estimated from the previous frame was used to filter the current frame so that filtering could be conducted in parallel with noise estimation. This speeds up the system thereby enabling real-time execution. The form of filtering windows was also modified to facilitate synchronization. The proposed structure was implemented on Virtex 4 XC4VLX60, occupying 66% of total slices with 80MHz of the maximum operation frequency.

• Journal of IKEEE
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• v.22 no.3
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• pp.522-531
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• 2018

A public-key cryptography processor EC-RSA was designed, which integrates a 224-bit prime field elliptic curve cryptography (ECC) defined in the FIPS 186-2 as well as RSA with 2048-bit key length into a single hardware structure. A finite field arithmetic core used in both scalar multiplication for ECC and exponentiation for RSA was designed with 32-bit data-path. A lightweight implementation was achieved by an efficient hardware sharing of the finite field arithmetic core and internal memory for ECC and RSA operations. The EC-RSA processor was verified by FPGA implementation. It occupied 11,779 gate equivalents (GEs) and 14 kbit RAM synthesized with a 180-nm CMOS cell library and the estimated maximum clock frequency was 133 MHz. It takes 867,746 clock cycles for ECC scalar multiplication resulting in the estimated throughput of 34.3 kbps, and takes 26,149,013 clock cycles for RSA decryption resulting in the estimated throughput of 10.4 kbps.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.11
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• pp.1135-1141
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• 2014

Performing wideband DDC while quantizing signal over a wide dynamic range and high speed sampling rate have primarily been implemented in a hardware such as, FPGA or ASIC because of time-consuming job. Real-time wideband DDC SW, even though signal environment changes, adapt to signal environment flexibly and can be reused. In addition, it has a lower price than the hardware implementation. In this paper, we study the system design that can be stored in real time designing a high-speed parallel processing architecture for SW-based wideband DDC. Finally, applying a Ping-Pong Buffering mechanism for receiving a signal in real time and CUDA for a high-speed signal processing, we verify wideband DDC design procedure that meets the signal processing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.45-53
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• 2007

In this paper, we propose an efficient hardware architecture for H.264/AVC CAVLC (Context-based Adaptive Variable Length Coding) encoding. Previous CAVLC architectures search all of the coefficients to find statistic characteristics in a block. However, it is unnecessary information that zero coefficients following the last position of a non-zero coefficient when CAVLC encodes residual coefficients. In order to reduce this unnecessary operation, we propose two techniques, which detect the first and last position of non-zero coefficients and arrange non-zero coefficients sequentially. By adopting these two techniques, the required processing time was reduced about 23% compared with previous architecture. It was designed in a hardware description language and total logic gate count is 16.3k using 0.18um standard cell library Simulation results show that our design is capable of real-time processing for $1920{\times}1088\;30fps$ videos at 81MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.9
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• pp.2153-2160
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• 2015

An analysis of hardware design conditions of moving object detection (MOD) algorithm is described, which is based on effective Gaussian mixture learning (EGML). A simulation model of EGML algorithm is implemented using OpenCV, and the effects of some parameter values on background learning time and MOD sensitivity are analyzed for various images. In addition, optimal design conditions for hardware implementation of EGML-based MOD algorithm are extracted from fixed-point simulations for various bit-widths of parameters. The proposed fixed-point model of the EGML-based MOD uses only half of the bit-width at the expense of the loss of MOD performance within 0.5% when compared with floating-point MOD results.

• KIPS Transactions on Computer and Communication Systems
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• v.9 no.12
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• pp.333-338
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• 2020

This paper proposes an augmented reality-based electronic circuit education system as a way for electronic circuit education, which is the basis of ICT convergence technology field. It consists of a hardware module that can identify the actual circuit and a mobile educational content that can check the current flow, input, output, and measured value by applying augmented reality technology. An experiment was conducted on image recognition, which is the main performance, for the purpose of stable operation of the system, and as the experimental method the recognition rate was measured by changing the distance between the hardware module and the mobile device to a certain interval. As a result of the experiment, the recognition rate was 100 percent at a distance of 25[Cm] or higher, and it was confirmed that the recognition rate decreased by 12% at a distance below 25[Cm], which can be said to be the effect of an error that results in image loss taken due to close distance. In the future, we plan to apply the education system presented in this paper to classes, which increases the efficiency of classes and improve students' interest and understanding of the subject.

• Journal of Institute of Control, Robotics and Systems
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• v.7 no.10
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• pp.837-842
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• 2001

In this paper, we design and implement the DC characteristic measurement system for semiconductor devices. The proposed system is composed of 4 SMU(Source and Measure Unit) channels. Various efforts in hardware and software have been made to reduce the measurement errors. Internal and external sources of errors in measurement system especially in pA range measurement have been identified and removed. Also, various digital signal processing techniques are developed. Calibration is executed under the control of microprocessor periodically. Experimental results show that the implemented system can measure the DC characteristic of semiconductor devices with less than 0.2% error in various voltage and current source/measurement range.

• Journal of Biomedical Engineering Research
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• v.30 no.1
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• pp.66-78
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• 2009

A mobile ultrasound scanner developed for use in point-of-care applications is introduced, which can not only provide ultrasound images but can also measure various bio-signals. The mobile ultrasound scanner is also designed to meet the demanding requirements for point-of-care diagnosis, such as battery-powered operation, portability in terms of size and weigh, and real-time wireless communications capability for remote diagnosis. To meet these requirements, an efficient beamforming method for high resolution imaging with a small number of active elements, a hardware efficient beamformer architecture, and echo processing algorithms with greatly reduced computational complexity have been developed. Experimental results show that the prototype mobile ultrasound scanner is fully functional and satisfies most of the design requirements.

• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.334-337
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• 2001

In this paper we implemented DDFS and gam-phase dectector which use output of DDFS or any sinusoidal signal input to broaden the usability of DDFS. DDFS is composed of a 32 bits phase accumulator, phase increment registers, ROM and several registers for controlling the operations. It generates the digital data for sine wave up to the half of the clock frequency. To reduce the ROM size and increase the speed, we adopt the algorithms based on Taylor's series expansion method. Data at sparse phase intervals are stored in ROM and sine data between intervals are calculated in hardware. Function of Gain-Phase Extraction consists of sine lookup of DDFS and the optimized multipliers.

• ETRI Journal
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• v.33 no.5
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• pp.661-669
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• 2011

In this paper, we propose an efficient soft-output signal detection method for spatially multiplexed multiple-input multiple-output (MIMO) systems. The proposed method is based on the ordered successive interference cancellation (OSIC) algorithm, but it significantly improves the performance of the original OSIC algorithm by solving the error propagation problem. The proposed method combines this enhanced OSIC algorithm with a multiple-channel-ordering technique in a very efficient way. As a result, the log likelihood ratio values can be computed by using a very small set of candidate symbol vectors. The proposed method has been synthesized with a 0.13-${\mu}m$ CMOS technology for a $4{\times}4$ 16-QAM MIMO system. The simulation and implementation results show that the proposed detector provides a very good solution in terms of performance and hardware complexity.