• Journal of the Korean Vacuum Society
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• v.10 no.4
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• pp.403-410
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• 2001

Acceleration in integration density and speed performance of ULSI circuits require miniaturization of CMOS and interconnections as well as higher current density capabilities for transistors. A leading candidate to substitute Al-alloy is Cu, which has lower resistivity and higher melting point. So we can expect much higher electromigration resistance. In this paper, we are going to explain the major features of EM for MOCVD Cu according to variant conditions. We compared the life time and activation energy of MOCVD Cu with those of I-beam Cu and AA in the same conditions. The electromigration experiments were performed with Cu/Al/TiN multilayer. Experimental results shows that the deposition rate and electromigration characteristics of Cu thin film were improved by the Al interlayer.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.1
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• pp.19-24
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• 2013

As CMOS technology is scaled down more aggressively, the reliability mechanism (or aging effect) caused by the diffusion of metal atoms along the conductor in the direction of the electron flow, also called electromigration (EM), has become a major reliability concern. With the present of EM, it is difficult to control the current flows of the MOSFET device and interconnect. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the EM effects on current of the nanoscale CMOS circuits are analyzed. Finally, this paper introduces an on-chip current measurement method providing lifetime electromigration management which are designed using 45-nm CMOS predictive technology model.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.4
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• pp.83-88
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• 2018

The electromigration (EM) tests were performed at $150^{\circ}C$ with $1.5{\times}10^5A/cm^2$ conditions in order to investigate the effect of non-conductive film (NCF) trap on the electrical reliability of Cu/Ni/Sn-Ag microbumps. The EM failure time of Cu/Ni/Sn-Ag microbump with NCF trap was around 8 times shorter than Cu/Ni/Sn-Ag microbump without NCF trap. From systematic analysis on the electrical resistance and failed interfaces, the trapped NCF-induced voids at the Sn-Ag/Ni-Sn intermetallic compound interface lead to faster EM void growth and earlier open failure.

• Journal of the Korean Vacuum Society
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• v.4 no.4
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• pp.380-385
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• 1995

AI-1%Si 박막배선에서 수명의 길이 의존성 및 EM에 대한 저항성을 절연보호막 및 온도에 대하여 관찰하였고 ICB증착된 Cu박막배선의 EM에 대한 저항성을 측정하여 진공 열증착된 Cu 박막배선과 비교하였다. 첫째, 절연보호막 처리된 AI-1%Si 박막배선에서 길이가 200$\mu$m에서 1200$\mu$m로 증가함에 따라 전류인가에 의한 평균 수명과 활성화에너지값이 감소하다가 임계길이서부터는 모두 포화되는 것으로 나타났다. 절연보호막 물질에 상관 없이 고온으로 갈수록 임계길이가 짧아지며 그것을 넘는 영역에서는 길에에 대한 의존성이 약해져 임계길이 이상을 갖는 박막배선인 경우 평균수명 및 활성화 에너지값은 길이보다 막특성에 의존하는 것으로 사료된다. 둘째, ICB 증착된 Cu 박막배선의 d.c.인가에 따른 평균 수명은 진공 열층착된 Cu 박막배선보다 길게 나왔으며 e.ectromigration에 대한 활성화 에너지값도 1.70eV로 1.33eV보다 높게 측정되어 EM에 대한 저항성이 증가한 것으로 나타났다.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.6
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• pp.436-441
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• 1999

Joule heating effect in EM(Electromigration) test were performed on a bend test structure. EM test is done under high current densities(1.0-2.5MA/cm2), which leads to joule heating. Since joule heating is added to the controlled oven(stress) temperature, themetal line temperature is higher than the stress temperature. The increase in the stress temperature due to joule heating is important because EM phenomena and metal line failure are related to the stress temperature. In this paper, metal line was stressed with a current density of 1.0 MA/$cm^2$, 1.5MA/$cm^2$, 2.0MA/$cm^2$, 2.5MA/$cm^2$, for 1200 sec and temperature increase due to joule heating was less than $10^{\circ}C$. Also it took 30 minutes for the metal line to equalized with oven temperature. Recommendations are given for the EM test to determine the initial resistance of EM test structure under stress temperature and current density.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.3
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• pp.81-88
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• 2019

In this study, the effects of graphene oxide (GO) addition on electromigration (EM) lifetime of Sn-3.0Ag-0.5Cu Pb-free solder joint between a ball grid array (BGA) package and printed circuit board (PCB) were investigated. After as-bonded, $(Cu,Ni)_6Sn_5$ intermetallic compound (IMC) was formed at the interface of package side finished with electroplated Ni/Au, while $Cu_6Sn_5$ IMC was formed at the interface of OSP-treated PCB side. Mean time to failure of solder joint without GO solder joint under $130^{\circ}C$ with a current density of $1.0{\times}10^3A/cm^2$ was 189.9 hrs and that with GO was 367.1 hrs. EM open failure was occurred at the interface of PCB side with smaller pad diameter than that of package side due to Cu consumption by electrons flow. Meanwhile, we observed that the added GO was distributed at the interface between $Cu_6Sn_5$ IMC and solder. Therefore, we assumed that EM reliability of solder joint with GO was superior to that of without GO by suppressing the Cu diffusion at current crowding regions.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.47-53
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• 2015

The effects of electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes on the in-situ intermetallics reaction and the electromigration (EM) reliability of Sn-3.0Ag-0.5Cu (SAC305) solder bump were systematically investigated. After as-bonded, $(Cu,Ni)_6Sn_5$ intermetallic compound (IMC) was formed at the interface of the ENIG surface finish at solder top side, while at the OSP surface finish at solder bottom side,$ Cu_6Sn_5$ and $Cu_3Sn$ IMCs were formed. Mean time to failure on SAC305 solder bump at $130^{\circ}C$ with a current density of $5.0{\times}10^3A/cm^2$ was 78.7 hrs. EM open failure was observed at bottom OSP surface finish by fast consumption of Cu atoms when electrons flow from bottom Cu substrate to solder. In-situ scanning electron microscope analysis showed that IMC growth rate of ENIG surface finish was much lower than that of the OSP surface finish. Therefore, EM reliability of ENIG surface finish was higher than that of OSP surface finish due to its superior barrier stability to IMC reaction.

• Journal of Korean Vacuum Science & Technology
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• v.5 no.1
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• pp.11-18
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• 2001

Dielectric passivation effects on the EM(electromigration) have been a great interest with recent ULSI and multilevel structure tends in thin film interconnections of a microelectronic device. SiO$_2$, PSG(phosphosilicate glass), and Si$_3$N$_4$ passivation materials effects on the EM resistance were investigated by utilizing widely used Al-1%Si thin film interconnections. A standard photolithography process was applied for the fabrication of 0.7㎛ thick 3㎛ wide, and 200㎛ ~1600㎛ long Al-1%Si EM test patterns. SiO$_2$, PSG, and Si$_3$N$_4$ dielectric passivation with the thickness of 300 nm were singly deposited onto the Al-1%Si thin film interconnections by using an APCVD(atmospheric pressure chemical vapor deposition) and a PECVD(plasma enhanced chemical vapor deposition) in order to investigate the passivation materials effects on the EM characteristics. EM tests were performed at the direct current densities of 3.2 $\times$ 10$\^$6/∼4.5 $\times$ 10$\^$6/ A/cm$^2$ and at the temperatures of 180 $\^{C}$, 210$\^{C}$, 240$\^{C}$, and 270$\^{C}$ for measuring the activation energies(Q) and for accelerated test conditions. Activation energies were calculated from the measured MTF(mean-time-to-failure) values. The calculated activation energies for the electromigration were 0.44 eV, 0.45 eV, and 0.50 eV, and 0.66 eV for the case of nonpassivated-, Si$_3$N$_4$passivated-, PSG passivated-, and SiO$_2$ passivated Al-1%Si thin film interconnections, respectively. Thus SiO$_2$ passivation showed the best characteristics on the EM resistance followed by the order of PSG, Si$_3$N$_4$ and nonpassivation. It is believed that the passivation sequences as well as the passivation materials also influence on the EM characteristics in multilevel passivation structures.

• Journal of the Korean Vacuum Society
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• v.11 no.4
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• pp.194-200
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• 2002

MOCVD(metal-organic chemical vapor deposition) copper thin film was annealed at various conditions and the eletrical properties and micro-structures were investigated to find the optimal annealing condition and its effect. Cu thin film annealed at Ar 1 torr, $400^{\circ}C$ had the most improved resistivity of 1.98 $\mu\Omega$cm, and texture; the ratio of $I_{(111)}/I_{(200)}$ was varied from 2.03 to 3.11, and Cu thin film annealed at Ar 1 torr, $450^{\circ}C$ had the largest grain size and uniformity. After the annealing, the EM(electromigration) test was followed to ensure the improved properties by annealing. Compare to other conditions, Cu patterns annealed at Ar 1 torr, $400 ^{\circ}C$ had the most improved properties when it came to the EM resistance, which was due to the low resistivity, the preferential evolution of texture to (111) plane, and the reduction of surface roughness of annealed copper film.

• Journal of Korean Vacuum Science & Technology
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• v.7 no.2
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• pp.39-44
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• 2003

Recent ULSI and multilevel structure trends in microelectronic devices minimize the line width down to a quarter micron and below, which results in the high current densities in thin film interconnections. Under high current densities, an EM(electromigration) induced failure becomes one of the critical problems in a microelectronic device. This study is to improve thin film interconnection materials by investigating the EM characteristics in PSG(phosphosilicate glass)/SiO$_2$ passivated Al-l%Si thin film interconnections. Straight line patterns, wide and narrow link type patterns, and meander type patterns, etc. were fabricated by a standard photholithography process. The main results are as follows. The current crowding effects result in the decrease of the lifetime in thin film interconnections. The electric field effects accelerate the decrease of lifetime in the double-layered thin film interconnections. The lifetime of interconnections also depends upon the current conditions of P.D.C.(pulsed direct current) frequencies applied at the same duty factor.