• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.97-98
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• 2006

High current behaviors of the grounded gate extended drain N-type metal-oxide-semiconductor field effects transistor (GG_EDNMOS) electro-static discharge (ESD) protection devices are analyzed. Simulation based contour analyses reveal that combination of BJT operation and deep electron channeling induced by high electron injection gives rise to the 2-nd on-state. Thus, the deep electron channel formation needs to be prevented in order to realize stable and robust ESD protection performance. Based on our analyses, general methodology to avoid the double snapback and to realize stable ESD protection is to be discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.08a
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• pp.19-24
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• 2002

Static electricity is an everyday phenomenon. There can be few of us who have not experienced a static shock after sliding across a car seat. Other static nuisance effects include the cling of some fabrics to the body, the sticking of a plastic document cover, or the attraction of dust to a TV or computer screen. However, static electricity has been a serious industrial problem. The age of electronics brought with it new problems associated with static electricity and electrostatic discharge. And, as electronic devices became faster and smaller, their sensitivity to ESD increased. In this work, We are study on the control technique of electo-static discharges using semiconductor circuits. Our circuits are prevented well to electrostatic shock or damages from triboelectric charging in cars everyday life.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.11a
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• pp.538-542
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• 1999

New methodology of parameter calibration is proposed for TCAD simulation of nMOSFET in ESD(Electro-Static Discharge) protection circuits. Recently, TLP(Transmission Line Pulsing) measurement has received great interest due to the ability of analyzing device characteristics when ESD pulse is applied to the ESD pulse is applied to the ESD protection circuits. This paper describes new methodology of analyizing TLP measurement, TCAD simulation, and parameter calibration.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.6
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• pp.35-40
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• 2008

High performance light emitting diodes(LEDs) have been developed using GaN-based materials grown on sapphire substrates in recent years. Although these LEDs are already commercially available, we have to consider electrostatic discharge(ESD) damage related to both basic materials of diode and miniaturization of LEDs. ESD damage is one of the important parameters influencing reliability of the light emitting devices. We investigated mass production of GaN-based LEDs suffered from ESD during production process and present the solutions in order to improve the ESD problem. Most of EDS problems were controlled by using instruments properly and improvement of the process circumstances as well.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.1
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• pp.1-6
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• 2009

The holding voltage of high-voltage devices under the snapback breakdown condition has been known to be much smaller than the operating voltage. Such characteristics cause high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used as the ESD(ElectroStatic Discharge) power clamp circuit. A new latchup-free design of the ESD power clamp circuit with stacked-bipolar devices is proposed and successfully verified in a $0.35{\mu}m$ 3.3V/60V BCD(Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the operating voltage. Proposed power clamp operates safely because of the high holding voltage. From the measurement on the devices fabricated using a $0.35{\mu}m$ BCD Process, it was observed that the proposed ESD power clamp can provide 800% higher ESD robustness per silicon area as compared to the conventional clamps with a high-voltage diode.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.51 no.4
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• pp.545-552
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• 2015

The main object of this study is to investigate the collection characteristics of an electro-static multi-staged impaction system, experimentally. The experiment is carried out to analyze the characteristics of pressure drop and collection efficiency for the present system with the experimental parameters such as the inlet velocity, stage number, applied voltage and shape of discharge electrode, etc. In results, the pressure drop is shown below $148mmH_2O$ lower than that of the conventional bag filter at inlet velocity 3.46 m/s and 5 stage. For 5 stage, the collection efficiencies are to be 97.4, 99.0% with the applied voltage 0 kV at the inlet velocity 2.07, 3.46 m/s, while 98.4, 99.9% with 40 kV of a sharp edge discharge electrode. Additionally, the present system is to be considered as an effective compact system for a removal of particulate pollutants from marine diesel engines due to much higher collection efficiency and appropriate pressure drop.

• Journal of IKEEE
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• v.27 no.3
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• pp.258-264
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• 2023

This paper proposes an LDO regulator with a built-in ESD (Electro Static Discharge) protection circuit to effectively operate and prevent destruction of the LDO (Low Drop Out) regulator according to the load current. The proposed LDO regulator can more effectively adjust the gate node voltage of the pass transistor according to the output voltage of the LDO regulator by using an additional feedback current circuit structure. In addition, it is expected to have high reliability for the ESD situation by embedding a new structure that increases the holding voltage by about 2V by reducing the current gain on the SCR loop by adding a P+ bridge to the existing ESD protection device.

• Journal of Applied Reliability
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• v.11 no.3
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• pp.251-265
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• 2011

Low-noise amplifier(LNA) is a component that amplifies the signal while lowering the noise figure of high-frequency signal. LNA holds a very important position in RF system so that it is widely used for telecommunication. Electro static discharge(ESD) is the most common cause of malfunction for low-powered components, such as Large Scale Integration and IC type LNA is weak in ESD. This thesis studies static effect of communication LNA. It analyzes ESD effect, which occurs within LNA circuit, and describes testing standard and methods. In order to find out LNA's susceptiblity to electro static, two well-recognized communication IC type LNA models were selected to be tested. Then static-induced malfunction was carefully analyzed and it suggests architectural problem and improvement from the LNA's ESD point of view.

• Journal of the Korea Convergence Society
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• v.8 no.8
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• pp.77-82
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• 2017

In the splay manufacturing process, conveyor systems are widely used for conveying panels. In this conveyor, a large number of grounding lines are used in order to prevent a product failure due to static electricity. In many cases, the grounding line is disconnected due to the rotation of the transporting roller or curling, leading to product failure. In order to solve such a problem, there is a growing need for a system capable of detecting disconnection of a ground wire in real time. Therefore, in this paper, we propose a disconnection monitoring system of ESD (Electro-Static Discharge) ground wire caused by friction between the conveyor drive part and the panel. The proposed system is a monitoring system that can detect disconnection and disconnection of ground wire using ATmega 2560 and Wheatstone Bridge circuit. It can detect disconnection of ground wire immediately and can take measures to reduce the defect rate due to static electricity. The system proposed in this paper is expected to be applicable to the production and test equipments of all industries where the ground wire is used.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1289-1294
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• 2008

Electrostatic discharge(ESD) phenomenon is a serious reliability concern. It causes approximately most of all field failures of IC. To quality the ESD immunity of IC product, there are some test methods and standards developed. ESD events have been classified into 3 models, which are HBM, MM and CDM. All the test methods are designed to evaluate the ESD immunity of IC products. This study provides an overview among ESD test methods on ICs and an efficient ESD stress method. We have estimated on all pin combination about the positive and negative ESD stress. We make out the weakest stress mode. This mode called a worst-case mode. We proposed that positive supply voltage pin and I/O pin combination is efficient because it is a worst-case mode.