• 한국항행학회논문지
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• 제21권3호
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• pp.287-293
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• 2017

본 논문은 균일한 임피던스를 갖는 출력 포트사이 전송선로의 전기적 길이를 다르게 함으로서 비대칭 Bagley 분배기 설계에 대한 내용을 서술하였다. 이 분배기는 입력 포트와 연결된 출력 포트의 전기적 길이만을 조정하여 출력 포트에 원하는 임의의 출력 비율을 얻을 수 있고, 모든 전송선로의 특성 임피던스는 균일한 것이 특징이다. 이러한 설계 방법을 사용하면 비대칭 출력을 얻을 수 있음에도 출력포트에는 임피던스 변환기를 사용하지 않는다. 이것을 증명하기 위해서 동작주파수 2 GHz에서 1:2:1 비율의 3차와 2:3:4:3:2 비율의 5차 비대칭 Bagley 분배기를 시뮬레이션과 제작하였다. 측정 결과는 시뮬레이션과 동일함을 확인하였다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• 제12권1호
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• pp.325-339
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• 2018

In this paper, we propose a joint adaptive combining and variable tap-length multiuser detector (MUD) for amplify-and-forward (AF) underwater acoustic cooperative interleave-division multiple access (IDMA) communication system. The proposed MUD jointly realizes tap-length adjustment, adaptive combining, and multiuser detection. In contrast to the existing methods, the proposed detector can adaptively combine the received signals from different nodes at destination, and does not need the assumption that full and perfect channel state information (CSI) of all the links at the receiver is known. Moreover, the proposed detector can adaptively adjust the tap coefficient vector and tap-length of each branch according to the specific channel profile of each branch. Simulation results validate the feasibility and show the advantages of the proposed detector against existing counterparts.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권1호
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• pp.1-11
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• 2004

A FinFET, a novel double-gate device structure is capable of scaling well into the nanoelectronics regime. High-performance CMOS FinFETs , fully depleted silicon-on-insulator (FDSOI) devices have been demonstrated down to 15 nm gate length and are relatively simple to fabricate, which can be scaled to gate length below 10 nm. In this paper, some of the key elements of these technologies are described including sub-lithographic pattering technology, raised source/drain for low series resistance, gate work-function engineering for threshold voltage adjustment as well as metal gate technology, channel roughness on carrier mobility, crystal orientation effect, reliability issues, process variation effects, and device scaling limit.

• Transactions on Electrical and Electronic Materials
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• 제16권3호
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.

• 제어로봇시스템학회논문지
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• 제2권2호
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• pp.67-72
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• 1996

This paper presents a parameter adaptive control law that stabilizes and asymptotically regulates any single-input, linear time-invariant, controllable and observable, discrete-time system when only the upper bounds on the order of the system is given. The algorithm presented in this paper comprises basically a nonlinear state feedback law which is represented by functions of the state vector in the controllable subspace of the model, an adaptive identifier of plant parameters which uses inputs and outputs of a certain length, and an adaptive law for feedback gain adjustment. A new psedu-inverse algorithm is used for the adaptive feedback gain adjustment rather than a least-square algorithm. The proposed feedback law results in not only uniform boundedness of the state vector to zero. The superiority of the proposed algorithm over other algorithms is shown through some examples.

• Journal of the Optical Society of Korea
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• 제18권2호
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• pp.101-109
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• 2014

In this paper, four apodization functions are proposed for silicon-on-insulator (SOI) strip waveguides with sidewall-corrugated gratings. The effects of apodization functions on the full width at half maximum (FWHM), the side-lobe level, and the reflectivity of the reflection spectrum are studied using the coupled-mode theory (CMT) and the transfer-matrix method (TMM). The results show that applying proposed apodization functions creates very good filtering characteristics. Among investigated apodized waveguides, the apodization functions of Polynomial and z-power have the best performance in reducing side-lobes, where the side-lobe oscillations are entirely removed. Four functions are also used for precise adjustment of the bandwidth. Simulation results show that the minimum and maximum values of the FWHM are 0.74 nm and 8.48 nm respectively. In some investigated functions, changing the apodization parameters decreases the reflectivity which is compensated by increasing the grating length.

• 대한전기학회논문지:시스템및제어부문D
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• 제52권12호
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• pp.689-695
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• 2003

Fault-tolerance is an important design criterion for robotic systems operating in hazardous or remote environments. This paper addresses the issue of tolerating a locked joint failure in gait planning for hexapod walking machines which have symmetric structures and legs in the form of an articulated arm with three revolute joints. A locked joint failure is one for which a joint cannot move and is locked in place. If a failed joint is locked, the workspace of the resulting leg is constrained, but hexapod walking machines have the ability to continue static walking. A strategy of fault-tolerant tripod gait is proposed and, as a specific form, a periodic tripod gait is presented in which hexapod walking machines have the maximum stride length after a locked failure. The adjustment procedure from a normal gait to the proposed fault-tolerant gait is shown to demonstrate the applicability of the proposed scheme.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1992년도 춘계학술대회 논문집
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• pp.86-90
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• 1992

We have studied the characteristics of n-and p-channel FETs with submicron channel length fabricated by twin-well process. Threshold voltage variation and potential distribution with channel ion implantation conditions and impurity profile of n-and p-channel region wee simulated using SUPREM-II and MINIMOS 4.0 simulater, P-channel FET had buried-channel in the depth of 0.15 $\mu\textrm{m}$ from surface by counter-doped boron ion implantation for threshold voltage adjustment. As a result of device measurement, we have obtained good drain saturation characteristics for 3.3 [V] opreation, minimized short channel effect with threshold voltage shift below 0.2[V], high punchthrough and breakdown voltage above 10[V] and low subthreshold value.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권9호
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• pp.547-555
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• 2005

A fault-tolerant gait of multi-legged robots with static walking is a gait which can maintain gait stability and continue its walking against an occurrence of a leg failure. This paper proposes fault-tolerant gait planning of a quadruped robot walking over a rough planar terrain. The considered fault is a locked joint failure, which prevents a joint of a leg from moving and makes it locked in a known position. In this Paper, two-phase discontinuous gaits are presented as a new fault-tolerant gait for quadruped robots suffering from a locked joint failure. By comparing with previously developed one-phase discontinuous gaits, it is shown that the proposed gait has great advantages in gait performance such as the stride length and terrain adaptability. Based on the two-phase discontinuous gait, quasi follow-the-leader(FTL) gaits are constructed which enable a quadruped robot to traverse two-dimensional rough terrain after an occurrence of a locked joint failure. During walking, two front legs undergo the foot adjustment procedure for avoiding stepping on forbidden areas. The Proposed wait planning is verified by using computer graphics simulations.

• 전자공학회논문지SC
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• 제42권3호
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• pp.1-10
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• 2005

본 논문에서는 기구학적 구속조건을 고려한 육각 보행 로봇의 새로운 내고장성 걸음새를 제안한다. 본 논문에서 고려하고 있는 고장은 관절고착고장으로 로봇 다리의 관절 하나가 어떤 위치에 고착되어서 보행이 끝날 때까지 움직일 수 없는 상태를 말한다. 본 논문에서는 먼저 육각 보행 로봇의 직선 보행을 위한 기존의 내고장성 걸음새가 고장 난 다리의 기구학적 구속조건에 따라서 교착 상태에 빠질 수도 있음을 해석적으로 증명한다. 그런 다음 이러한 교착 상태를 회피하기 위해서 새로운 내고장성 걸음새 계획을 제안한다. 제안하는 내고장성 걸음새는 다리의 궤적을 변경함으로써 고장 난 다리가 야기하는 교착 상태에서 벗어날 수 있으며, 기존 내고장성 걸음새의 다리 움직임 순서와 보폭을 그대로 유지한다. 제안한 걸음새 계획의 우수성을 입증하기 위해서 평탄 지형에서 정상적인 걸음새로 걷고 있는 육각 보행 로봇이 고장이 일어난 후 제안한 걸음새 계획을 이용하여 교착 상태에서 벗어나 내고장성 걸음새로 전이하는 사례 연구도 기술한다.