• 제목/요약/키워드: Electrical insulator

검색결과 1,346건 처리시간 0.061초

Properties of Dy-doped $La_2O_3$ buffer layer for Fe-FETs with Metal/Ferroelectric/Insulator/Si structure

  • Im, Jong-Hyun;Kim, Kwi-Jung;Jeong, Shin-Woo;Jung, Jong-Ill;Han, Hui-Seong;Jeon, Ho-Seung;Park, Byung-Eun
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.140-140
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    • 2009
  • The Metal-ferroelectric-semiconductor (MFS) structure has superior advantages such as high density integration and non-destructive read-out operation. However, to obtain the desired electrical characteristics of an MFS structure is difficult because of interfacial reactions between ferroelectric thin film and Si substrate. As an alternative solution, the MFS structure with buffer insulating layer, i.e. metal-ferroelectric-insulator-semiconductor (MFIS), has been proposed to improve the interfacial properties. Insulators investigated as a buffer insulator in a MFIS structure, include $Ta_2O_5$, $HfO_2$, and $ZrO_2$ which are mainly high-k dielectrics. In this study, we prepared the Dy-doped $La_2O_3$ solution buffer layer as an insulator. To form a Dy-doped $La_2O_3$ buffer layer, the solution was spin-coated on p-type Si(100) wafer. The coated Dy-doped $La_2O_3$ films were annealed at various temperatures by rapid thermal annealing (RTA). To evaluate electrical properties, Au electrodes were thermally evaporated onto the surface of the samples. Finally, we observed the surface morphology and crystallization quality of the Dy-doped $La_2O_3$ on Si using atomic force microscopy (AFM) and x-ray diffractometer (XRD), respectively. To evaluate electrical properties, the capacitance-voltage (C-V) and current density-voltage (J-V) characteristics of Au/Dy-doped La2O3/Si structure were measured.

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가공송전선로 애자 적용실태와 향후 전망 (Insulator application and prospect)

  • 김우겸;민병욱;김태영;위화복;최진성;이북창
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2009년도 제40회 하계학술대회
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    • pp.327_328
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    • 2009
  • The insulator being used for transmission line is to mount the charged conductor on the tower or other supports. The insulators are classified according to its material: porcelain, glass and polymer. Polymer insulators are also called as composite insulator or non ceramic insulator (NCI). Insulators are a major element of a power transmission system. Since a faulty insulator can lead to a wide spreading blackout, it must have sufficient mechanical and electrical strength. It must be durable, have high electrical insulation and be able to withstand a leakage current. It must also be able to withstand the toughest weather conditions. In Korea, porcelain insulators have been used widely. However, to make compact equipment and keep up with global trends, we have enhanced domestic production of polymer insulator and are encouraging its applications. Accordingly, this thesis will look at types of insulators, use and trends, and prospects of insulators application in the field.

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폴리머 현수애자의 신뢰성 평가 및 복합가속열화 방법 (Reliability Evaluation Criteria and Multi-Stress Aging Test for Polymer Insulator)

  • 박효열;강동필;안명상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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    • pp.469-472
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    • 2004
  • There have been numerous accelerated aging laboratory tests for evaluating suitability of polymeric materials and devices. Aging test for materials and its full scale device has been conducted, but poor correlation of aging test such as service experience were observed. Service experience plays a key role in the utility section of composite insulators. A meaningful and reliable accelerated aging test is needed for evaluating composite insulator. During the service these insulators are subjected to aging stress such as humidity, pollution, and electrical field, and erosion and tracking of the weathershed occurs. This paper presents the criteria of reliability evaluation and evaluation facilities for 22.9 kV suspension composite insulator. We adopt the criteria of reliability evaluation consist of two test methods. One is CEA tracking wheel test for examining the tracking and erosion performance of composite insulator. The other is multi-stress aging test for examining effects of environmental factors such as UV, temperature, humidity, etc on composite insulator.

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송전용 36,000 lbs 자기애자의 수명 예측 연구 (A Study of Life Prediction Assessment of T/L 36,000 Ibs Porcelain Insulators)

  • 최인혁;최연규;이동일;이원교;강병규;박준호
    • 한국전기전자재료학회논문지
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    • 제20권7호
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    • pp.636-644
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    • 2007
  • 36,000lbs porcelain insulators of D-1995, D-1997 and D-2002 investigated mechanical and electrical qualities, where is process of using in the Korea 154 kV transmission lines. It analyzes the cause of the elapse of a year aging of the transmission insulators. Weibull distribution function, product quality and uniform quality, etc. investigated for prediction to extant life of insulator. It calculate change as statistical elapse of a year through product qualities of used insulator and new insulator, uniform equality and uniformity of insulator. In case of D-1995 year used insulator, it decided to badness decline index k by 0.0237, badness quality index by 1.0 and 3.0. Result of extant confidence life Ym was calculated that remain each 4 yens and 0.7 yens that uniformity index is considered. Extant life of D-1997 and D-2002 insulators Predicted by about 40 years.

Hybrid Insulator Organic Thin Film Transistors With Improved Mobility Characteristics

  • Park, Chang-Bum;Jin, Sung-Hun;Park, Byung-Gook;Lee, Jong-Duk
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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    • pp.1291-1293
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    • 2005
  • Hybrid insulator pentacene thin film transistors (TFTs) were fabricated with thermally grown oxide and cross-linked polyvinylalcohol (PVA) including surface treatment by dilute ploymethylmethacrylate (PMMA) layers on $n^+$ doped silicon wafer. Through the optimization of $SiO_2$ layer thickness in hybrid insulator structure, carrier mobility was increased to above 35 times than that of the TFT only with the gate insulator of $SiO_2$ at the same transverse electric field. The carrier mobility of 1.80 $cm^2$/V-s, subthreshold swing of 1.81 V/decade, and $I_{on}$/ $I_{off}$ current ratio > 1.10 × $10^5$ were obtained at low bias (less than -30 V) condition. The result is one of the best reported performances of pentacne TFTs with hybrid insulator including cross-linked PVA material at low voltage operation.

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표면 처리한 $SiO_2$를 게이트 절연막으로 하는 박막 트랜지스터의 특성 연구 (A STUDY ON THE ELECTRICAL CHARACTERISTICS OF ORGANIC THIN FILM TRANSISTORS WITH SURFACE-TREATED GATE DIELECTRIC LAYER)

  • 이재혁;이용수;박재훈;최종선;김유진
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2000년도 추계학술대회 논문집 학회본부 C
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    • pp.455-457
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    • 2000
  • In this work the electrical characteristics of organic TFTs with the semiconductor-insulator interfaces, where the gate dielectrics were treated by the two methods which are the deposition of Octadecyltrichlorosilane (OTS) on the insulator and rubbing the insulator surface. Pentacene is used as an active semiconducting layer. The semiconductor layer of pentacene was thermally evaporated in vacuum at a pressure of about $2{\times}10^{-7}$ Torr and at a deposition rate of $0.3{\AA}/sec$. Aluminum and gold were used for the gate and source/drain electrodes. OTS is used as a self-alignment layer between $SiO_2$ and pentacene. The gate dielectric surface was rubbed before pentacene is deposited on the insulator. In order to confirm the changes of the surface morphology the atomic force microscopy (AFM) was utilized. The characteristics of the fabricated TFTs are measured to clarify the effects of the surface treatment.

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Effects of Self-assembled Monolayer on PVP Gate Insulator for Organic Thin Film Transistors

  • Jang, Sun-Pil;Park, J.H.;Choi, J.S.;Ko, K.Y.;Sung, M.M.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.1044-1045
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    • 2004
  • In this work, the characteristics of organic thin film transistors (OTFTs) with self-assembled monolayers (SAMs) on polymeric gate insulator have been investigated. The SAMs were formed using atomic layer deposition (ALD) method onto gate insulator. Upon the investigations, it was observed that SAMs modify the wettability of polymeric insulator and influence the growth of subsequent organic semiconductor, and thereby, electric conductivity and roughness of the pentacene film are improved.

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Strained-Silicon-on-Insulator (sSOI) 기판을 이용한 Capacitorless 1-Transistor DRAM 소자 (A Capacitorless 1-Transistor DRAM Device using Strained-Silicon-on-Insulator (sSOI) Substrate)

  • 김민수;오준석;정종완;이영희;정홍배;조원주
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2009년도 하계학술대회 논문집
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    • pp.95-96
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    • 2009
  • A fully depleted capacitorless 1-transistor dynamic random access memory (FD 1T-DRAM) based on a sSOI strained-silicon-on-insulator) wafer was investigated. The fabricated device showed excellent electrical characteristics of transistor such as low leakage current, low subthreshold swing, large on/off current ratio, and high electron mobility. The FD sSOI 1T-DRAM can be operated as memory device by the floating body effect when the substrate bias of -15 V is applied, and the FD sSOI 1T-DRAM showed large sensing margin and several milli seconds data retention time.

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Electrical Characteristics of Organic Thin-film Transistors with Polyvinylpyrrolidone as a Gate Insulator

  • Choi, Jong-Sun
    • Journal of Information Display
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    • 제9권4호
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    • pp.35-38
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    • 2008
  • This paper reports the electrical characteristics of polyvinylpyrrolidone (PVPy) and the performance of organic thin-film transistors (OTFTs) with PVPy as a gate insulator. PVPy shows a dielectric constant of about 3 and contributes to the upright growth of pentacene molecules with $15.3\AA$ interplanar spacing. OTFT with PVPy exhibited a field-effect mobility of 0.23 $cm^2$/Vs in the saturation regime and a threshold voltage of -12.7 V. It is notable that there was hardly any threshold voltage shift in the gate voltage sweep direction. Based on this reliable evidence, PVPy is proposed as a new gate insulator for reliable and high-performance OTFTs.

Latch up 전후의 SOI(SOS) LIGBT 구조에서의 열전도 특성 분석 (The thermal conductivity analysis of the SOI/SOS LIGBT structure)

  • 김제윤;김재욱;성만영
    • 한국컴퓨터산업교육학회:학술대회논문집
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    • 한국컴퓨터산업교육학회 2003년도 제4회 종합학술대회 논문집
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    • pp.79-82
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    • 2003
  • The electrothermal simulation of high voltage LIGBT(Lateral Insulated Gate Bipolar Transistor) in thin Silicon on insulator (SOI) and Silicon on sapphire (SOS) for thermal conductivity and sink is performed by means of MEDICI. The finite element simulations demonstrate that the thermal conductivity of the buried oxide is an important parameter for the modeling of the thermal behavior of silicon-on-insulator (SOI) devices. In this paper, using for SOI LIGBT, we simulated electrothermal for device that insulator layer with $SiO_2$ and $Al_2O_3$ at before and after latch up to measured the thermal conductivity and temperature distribution of whole device and verified that SOI LIGBT with $Al_2O_3$ insulator had good thermal conductivity and reliability.

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