• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.23 no.1
• /
• pp.29-33
• /
• 2010

As the demands for the higher data transmission speed and capacity as well as integration density grow throughout the network, much works have being done in order to integrate the Electrical PCB with Optical PCB. However, one of the most troublesome problems in the commercial bonding process is to need the high temperature for the bonding. Due to the high temperature bonding process, lots of side problems are followed such as warpage and crack, etc. In this paper, we tried to develop the new bonding technology with low temperature around $100^{\circ}C$. As a result of this study, the PCB bonding technology with high bonding strength is demonstrated with the value of bonding strength from 7 to 8 MPa at the temperature of $100^{\circ}C$.

• Proceedings of the KIEE Conference
• /
• 2009.07a
• /
• pp.1501_1502
• /
• 2009

Plasma treatment time was optimized to maximize the bonding strength between silicon and quartz. Bonding strength between the silicon and quartz is related to a surface energy which can be calculated by contact angle measurement. It was found that optimized time to get maximized surface energy was 15 sec. Silicon and quartz wafers were treated with $O_2$ plasma under different time splits and then bonded together. Bonding strength of the bonded wafers was measured by shear test. It was verified that the highest bonding strength was obtained when the silicon and quartz wafers were treated for 15 seconds. The maximum bonding strength exceeded the fracture strength of silicon.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2009.06a
• /
• pp.385-386
• /
• 2009

This paper deals with assessment of equipotential bonding and electrical continuity in Buinding by investigation on the spot at construction site. The assessment was carried out for continuity of steelwork in reinforced concrete structure, bonding conductor, protective conductor. A new grounding system based on international standards includes unity grounding system, structure grounding utilizing steel reinforced concrete, equipotential bonding, use of surge protective device.

• Proceedings of the KIEE Conference
• /
• 2008.07a
• /
• pp.1480-1481
• /
• 2008

In this paper, we present surface treatments for achieving bonds between PMMA and PDMS substrates. Silane primer is used for the formation of hydroxyl group on PMMA surfaces. The formed hydroxyl groups enhance the bonding strength of PDMS-PMMA substrates without channel clogging and structure deformation. The bonding strength on the different surface treatments (include oxygen plasma, 3-APTES, and corona discharge) is evaluated to find optimal bonding condition. The maximum bonding strength at the optimal surface treatment is over 300 kPa. The surface treatment using silane primer can be used to the bonding process of Micro-TAS and Lab-on-a-Chip.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.22 no.8
• /
• pp.625-631
• /
• 2009

In this thesis, lateral thermosonic bonding with ACFs was investigated as a process to make high reliability joints for FPD fabrication. Conditions for thermosonic and thermocompression bonding with ACFs were determined and used to make specimens in a driving test jig for testing of bond reliability by thermal shock. The results showed that thermosonic bonding temperature of $199\;^{\circ}C$ and bonding time of 1s produced bonds with good reliability. Additionally, thermosonic bonding temperature and time were reduced and thermal shock test results compared to this proposed curing condition. It is concluded that theromosonic bonding with ACFs can be effectively applied to reduce bonding temperature and time compared with that of thermocompression bonding.

• Journal of the Microelectronics and Packaging Society
• /
• v.27 no.1
• /
• pp.17-24
• /
• 2020

As an interconnect scaling faces a technical bottleneck, the device stacking technologies have been developed for miniaturization, low cost and high performance. To manufacture a stacked device structure, a vertical interconnect becomes a key process to enable signal and power integrities. Most bonding materials used in stacked structures are currently solder or Cu pillar with Sn cap, but copper is emerging as the most important bonding material due to fine-pitch patternability and high electrical performance. Copper bonding has advantages such as CMOS compatible process, high electrical and thermal conductivities, and excellent mechanical integrity, but it has major disadvantages of high bonding temperature, quick oxidation, and planarization requirement. There are many copper bonding processes such as dielectric bonding, copper direct bonding, copper-oxide hybrid bonding, copper-polymer hybrid bonding, etc.. As copper bonding evolves, copper-oxide hybrid bonding is considered as the most promising bonding process for vertically stacked device structure. This paper reviews current research trends of copper bonding focusing on the key process of Cu-SiO₂ hybrid bonding.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1999.05a
• /
• pp.370-373
• /
• 1999

Si direct bonding (SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on- pre treatment conditions in Si wafer direct bonding, The paper resents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, applied pressure and annealing temperature(200~ 100$0^{\circ}C$) after pre-bonding. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera, respectively, Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding(Min 2.4kgf/$\textrm{cm}^2$~ Max : 14.kgf/$\textrm{cm}^2$)

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.30 no.10
• /
• pp.615-624
• /
• 2017

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.16 no.5
• /
• pp.365-371
• /
• 2003

We prepared silicon on insulator(SOI) wafer pairs of Si/1800${\AA}$ -SiO$_2$ ∥ 1800${\AA}$ -SiO$_2$/Si using water direct bonding method. Wafer pairs bonded at room-temperature were annealed by a normal furnace system or a fast linear annealing(FLA) equipment, and the micro-structure of bonding interfaces for each annealing method was investigated. Upper wafer of bonded pairs was polished to be 50 $\mu\textrm{m}$ by chemical mechanical polishing(CMP) process to confirm the real application. Defects and bonding area of bonded water pairs were observed by optical images. Electrical and mechanical properties were characterized by measuring leakage current for sweeping to 120 V, and by observing the change of wafer curvature with annealing process, respectively. FLA process was superior to normal furnace process in aspects of bonding area, I-V property, and stress generation.

• Proceedings of the KIEE Conference
• /
• 2005.11a
• /
• pp.30-32
• /
• 2005

This paper reports on an LTCC-based packaging method using Au/Sn eutectic bonding process for RF MEMS applications. The proposed packaging structure was realized by a micromachining technology. An LTCC substrate consists of metal filled vertical via feedthroughs for electrical interconnection and Au/Sn sealing rim for eutectic bonding. The LTCC capping substrate and the glass bottom substrate were aligned and bonded together by a flip-chip bonding technology. From now on, shear strength and He leak rate will be measured then the fabricated package will be compared with the LTCC package using BCB adhesive bonding method which has been researched in our previous work.