• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.415-418
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• 2004

This paper describes a VLSI implementation of BLAST detection for MIMO-OFDM systems. To achieve high speed requirement, we propose the fully pipeline architecture for BLAST structure. This design is implemented using $0.18{\mu}m$ CMOS technology. For a 4-transmit and 4-receive antennas system, it takes $7.5{\mu}s$ to calculate nulling vector and detection order from 48 channel matrixes.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.423-424
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• 2008

The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.924-930
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• 1989

This paper presents the design of simple robust controller for a class of uncertain multivariable systems. We introduce switching dynamics instead of switching logics unlike variable structure control scheme. Also, we can construct the continuous control law from this switching dynamics and consequently remove the chattering motion. The dynamic equations of the range-space of a switching surface matrix C and uniform ultimate boundedness in the presence of parameter uncertainties are described mathematically.

• Proceedings of the IEEK Conference
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• 2000.11a
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• pp.53-56
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• 2000

In this paper, the architecture for the residential gateway is designed for the traffic statistics of home environment. The suitability of 10 Mbps power line communication is investigated for the control and the video data distribution through simulation. The design issues are discussed for a residential gateway and the network design that is based on the power line communication is presented. Traffic models are established from the actual traffic traces. They are used for performance evaluation of residential networks.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.922-924
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• 1992

This paper presents a CAE(Computer Aided Engineering)system for solving electrostatic field problems by means of a small size computer such as a personal computer. The system software operated on the personal computer is composed of a CAD(Computer aided Design), electric field analysis by using FEM(Finite Element Method)and DB(Data Base)of insulating materials. In addition, we discuss an application of the system to analyzing electric field such as parallel plate electrodes with an insulation spacer, which result suggests that the visualization of electric field distribution and tolerance for insulation strength enables us to assure a simplified evaluation of the insulating design.

• ETRI Journal
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• v.33 no.3
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• pp.393-400
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• 2011

A systematic approach for the design of two-stage class AB CMOS unity-gain buffers is proposed. It is based on the inclusion of a class AB operation to class A Miller amplifier topologies in unity-gain negative feedback by a simple technique that does not modify quiescent currents, supply requirements, noise performance, or static power. Three design examples are fabricated in a 0.5 ${\mu}m$ CMOS process. Measurement results show slew rate improvement factors of approximately 100 for the class AB buffers versus their class A counterparts for the same quiescent power consumption (< 200 ${\mu}W$).

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.860-861
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• 2007

This paper deals with optimum design criteria to minimize torque ripple of concentrated winding Synchronous Reluctance Motor (SynRM) using Response Surface Methodology (RSM). The feasibility of using RSM with the finite element method(FEM) in practical engineering problem is investigated with computational examples and comparison between the fitted response and the results obtained from an analytical solution according to the design variables of stator and rotor in concentrated winding SynRM (6slot).

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.343-346
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• 2000

When a feedback bridging fault is activated, oscillation may be generated in output signal lines. If the oscillation is generated, the fault may not be detected by logic testing. Thus, in the past we proposed a current sensor to detect feedback bridging faults by supply current testing. The sensor circuit design requires the maximum frequency of oscillation which is generated when feedback bridging fault is excited as a specification. In this paper, an estimation method of the oscillation frequency is proposed. Also, it is shown by some experiments that the frequency obtained by the method can be used for the sensor design.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.351-354
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• 2000

In the past, we proposed an IDDQ testable design method for static CMOS PLA circuits. All bridging faults can be detected in NOR planes of our testable designed PLA circuits by IDDQ testing with 4 kinds of test input vectors which are independent of the logical functions to be realized. However, the testable designed PLA circuits consume large power in the normal operation. In this paper, a new IDDQ testable design method is proposed and evaluated by some experiments. The experimental results show that the PLA circuit designed with our method can work with low power consumption than the previous one.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1882-1885
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• 2002

This paper shows design of maximal-period sequences with prescribed constant auto-correlation values based on one-dimensional (1-D) maps with (mite bits. We construct such 1-D maps based on piecewise linear onto chaotic maps. Theoretical analyses and some design examples are given.