• International Journal of Aeronautical and Space Sciences
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• v.7 no.2
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• pp.42-49
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• 2006

In this paper, an efficient piezoelectric passive damper is newly devised to suppress the multi-mode vibration of plates. To construct the passive damper, the piezoelectric materials are utilized as energy transformer, which can transform the mechanical energy to electrical energy. To dissipate the electrical energy transformed from mechanical energy, multiple resonant shunted piezoelectric circuits are applied. The dynamic governing equations of a coupled electro-mechanical piezoelectric with multiple piezoelectric patches and multiple resonant shunted circuits is derived and solved for the one edge clamped plate. The equations of motion of the piezoelectrics and shunted circuits as well as the plate are discretized by finite element method to estimate more exactly the effectiveness of the piezoelectric passive damper. The method to find the optimal location of a piezoelectric is presented to maximize effectiveness for desired modes. The electro-mechanical coupling term becomes important parameter to select the optimal location.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.582-584
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• 1999

Generator has synchronized with power Network after build-up output voltage. In order to prevent a current surge when synchronizing, the conditions such as identical no-load voltages identical no-load frequencies and identical phase positions must be met between generator voltage and network voltage. Hydro-Pump generators or Gas-turbine generators, Co-generation Generators that serve peak load of network are synchronized many times. So, Automatic Synchronizing Circuits are very important service. This report apply Diagnosis methods the Automatic Synchronizing Circuits(Device) by developing simulator.

• Electrical & Electronic Materials
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• v.8 no.3
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• pp.254-260
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• 1995

A method is described for the design and fabrication of the sensor interface circuits on the Clark electrodes for the dissolved oxygen(DO). The discussion includes a method for the +5 V single-supply driving for the sensor circuits, which has low power comsumption for the front-end electronics. DO probe under test is composed of the Clark electrode with silver anode, gold cathode and the electrolyte of half saturated KCI solution and the FEP teflon memtrance for the oxygen penetration. Typical polarograms for the DO probes by using this sensor circuit reveals high accuracy over 99% of the I to V conversion. Partial pressure of oxygen obtained from the polarograms are well suited to the results calculated. It is expected that the proposed sensor circuits can be utilized into the customized IC for the battery-driven small-size DO meters.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.161-161
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• 2010

In order to achieve low power consumption and the uniform power spectrum of LED BLU (Back Light Unit) system, new circuits with a 2 stage L-C (Inductor-Capacitor) coupler have been proposed. From the simulation results based on our proposed model, the ripple power of the L-C regulation-embedded BLU circuit shows a dramatic reduction by more than 89.3% as compared to the normal BLU (without L-C circuits). This indicates that the proposed circuit is very promising for the realization of high-efficiency BLU circuits.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.1
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• pp.22-27
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• 2004

BiCMOS circuit consist of CMOS part which constructs logic function, and bipolar part which drives output load. In BiCMOS circuits, transistor stuck-open faults exhibit delay faults in addition to sequential behavior. In this paper, proposes a method for efficiently generating test pattern which detect stuck-open in BiCMOS circuits. In proposed method, BiCMOS circuit is divided into pull-up part and pull-down part, using structural property of BiCMOS circuit, and we generate test pattern using set theory for efficiently detecting faults which occured each divided blocks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.215-220
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• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.539-542
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• 1987

This paper presents driving circuits technology to enable high speed drive of MOSFET, IGBT(Insulated Gate Bipolar Transistor) and SIT(Static Induction Transistor). In addition to, it demonstrates application circuits(high frequency resonant type inverters, ultrasonic power supply etc.) using the, developing drive circuits.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.4
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• pp.134-139
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• 1984

This paper presents the computer program to design the synchronous sequential logic circuit. The computer program uses the MASK method to get the circuit of optimal cost. The computer program takes as an input, the minimal reduced state transition table where each state has its internal code. As an output,the optimal design of synchronous sequential logic circuit is generated for each flipflop type of JK,T,D, and RS respectively. And these circuits for 4 flipflop types are evaluated and sorted in ascending order of their costs, so that the user can select the proper flipflop type and its circuit. Furthermore,the proposed computer program may be applied to state assignment with its facility of cost evaluation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.353-356
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• 1996

Ultra-high-speed analog and digital ICs (integrated circuits) fur 10Gbit/sec optical communication systems have been designed, fabricated and analyzed in this research. These circuits, which are laser diode (LD) driver, pre-amplifier, automatic gain controlled (AGC) amplifier, limiting amplifier and decision circuit, have been implemented with AIGaAs/GaAs heterojunction bipolar transistors (HBTs). The optimized AIGaAs/GaAs HBTs for the 10Gbps circuits in this work showed the cutoff and maximum oscillation frequencies of 65㎓ and 53㎓, respectively. It is demonstrated in this paper that the 10Gbps optical communication system can be realized with the ICs designed and fabricated using AlGaAs/GaAs HBTs.