• Journal of Electrical Engineering and Technology
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• v.8 no.3
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• pp.565-571
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• 2013

This paper presents an effective method to improve efficiency of switched reluctance motor by optimizing energy conversion loop. A nonlinear analytical model which takes saturation account is developed to calculate inductance and flux-linkage. The flux-linkage curve is studied to calculate the co-energy increment to obtain the optimum exciting current. For a given cross-section, the exciting current at which co-energy increment is maximum was found to be constant while stack length varies. Then the energy conversion loop was optimized by varying the stack length and turns of windings. The constraints during optimization were that motor was excited by the maximum increment co-energy current and the energy in the loop was determined by rated power of motor. Dynamic finite element analysis was used to evaluate the efficiency of various models and the comparison of results shows promising effects of the proposed method. Experiment was also conducted to validate the simulation result.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.233-236
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• 2002

The solution for PFC(Power Factor Correction), as a regulation in energy Policy, is becoming a hot Issue in every country because of the shortage of electrical energy. Therefore, a new improved idea for PFC problem has been introduced in this study. A lot of merits, effective cost by simple circuit, reduced PCB size, lighter than reactor in the view of weight, lower level of screen noise by leakage inductance in CTV applications, have been stated by comparing to the earlier method of using a Reactor. All test results in this statement were done by using a power device of STR-G9600 series based on the real load condition of color television. furthermore, the study shows that the test results also meets the IEC-1000-3-2 class D, which regulates the PFC when input power of a set is more than 75watts. More improved PFC in other applications hopes to be implemented by using the proposed method.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.724-729
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• 1998

In general, a single-phase current-fed PWM inverter using IGBTs has some unique advantages for small scale distributed utility-interactive power supply system as compared with voltage-fed PWM inverter. In particular, this is more suitable and acceptable for a non-isolated type utility-interactive power conditioner, which is going to be widely used for residential solar photovoltaic (PV) power generation system in Japan. However, this current-fed PWM inverter has a significant disadvantage. The output current of this inverter includes large harmonic contents when the inductance of smoothing reactor in its DC side is not large enough to eliminate its current ripple components of this inverter. In order to overcome this problem, a new conceptual pulse area modulation scheme for this inverter is introduced in difference with conventional PWM strategy. This paper presents a new effective control implementation of this PV power conditioner which is able to reduce the harmonic component in the output current produced by the single-phase current-fed PWM inverter even when the ripple current in the smoothing DC reactor is relatively large. The operating principle of the proposed control strategy introdued for this inverter system is described, and its simulation results are evaluated and discussed herein.

• Journal of Power Electronics
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• v.17 no.5
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• pp.1268-1277
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• 2017

Three-phase pulse width modulation (PWM) rectifiers are usually designed under the assumption of ideal ac power supply and input inductance. However, non-ideal circuit parameters may lead to a voltage collapse of PWM rectifiers. This paper investigates the mechanism of voltage collapse in three-phase PWM rectifiers. An analytical stability boundary expression is derived by analyzing the equilibrium point of the averaging state space model, which can not only accurately locate the voltage collapse boundary in the circuit parameter domain, but also reveal the essential characteristic of the voltage collapse. Results are obtained and compared with those of the trial-error method and the Jacobian method. Based on the analysis results, the system parameters can be divided into two categories. One of these categories affects the critical point, and other affects only the instability process. Furthermore, an effective control strategy is proposed to prevent a vulnerable system from being driven into the instability region. The analysis results are verified by the experiments.

• Journal of Information Display
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• v.3 no.2
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• pp.26-30
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• 2002

Large area plasma source has been built for LCD etcher by an array of $2{\times}2$ ICP sources. Since only one RF power supply and one impedance matching network is used in this configuration, any difference in impedances of unit RF antennas causes unbalanced power delivery to the unit ICP. In order to solve this unavoidable unbalance, unit antenna is designed to have a movable tap, with which the inductance of each unit can be adjusted individually. The plasma density becomes symmetric and etch rate becomes more uniform with the impedance adjustment. The concept of adding axial time-varying magnetic field to the single ICP source is applied to the array ICP source, and is found to be effective in terms of etch rate and uniformity.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.2
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• pp.110-113
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• 2008

Embedded capacitor technology is one of the effective packing technologies for further miniaturization and higher performance of electric packaging system. In this paper, the embedded capacitors were simulated and fabricated in 8-layered printed circuit board employing standard PCB processes. The composites of barium titanante($BaTiO_3$) powder and epoxy resin were employed for the dielectric materials in embedded capacitors. Theoretical considerations regarding the embedded capacitors have been paid to understand the frequency dependent impedance behavior. Frequency dependent impedance of simulated and fabricated embedded capacitors was investigated. Fabricated embedded capacitors have lower self resonance frequency values than that of the simulated embedded capacitors due to the increased parasitic inductance values. Frequency dependent capacitances of fabricated embedded capacitors were well matched with those of simulated embedded capacitors from the 100MHz to 10GHz range. Quality factor of 20 was observed and simulated at 2GHz range in the 10 pF embedded capacitors. Temperature dependent capacitance of fabricated embedded capacitors was presented.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.75-82
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• 2006

In this paper, we design the meander line inductors with high sensitivity and high quality factor(Q) using high characteristic impedance of aperture ground plate. Sensitivity as a frequency is new defined by variation of effective inductance per analysis frequency range instead of self resonance frequency (SRF). An equivalent lumped circuit is derived to explain the characteristic of high frequency inductor. The 4 nH meander line inductor with aperture ground plate has 0.45 nH/GHz of good sensitivity and 86 of Q at 0.7 GHz.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.51-57
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• 2013

The current expanding mobile markets incessantly demands small form factor, low power consumption and high aggregate throughput for silicon-level integration such as memory to logic system. One of emerging solution for meeting this high market demand is 3D through silicon stacking (TSS) technology. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. In addition, this technology inherently help increase number of IOs and shorten interconnect length. With those benefits, however, potential signal and power integrity risks are also elevated; increase in PDN inductance, channel loss on substrate, crosstalk and parasitic capacitance. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28 nm node TSV test vehicles were fabricated by the foundry and assembled. Successful integration of memory wide IO chip with less than a millimeter package thickness form factor was achieved. For this successful integration, we discussed potential signal and power integrity challenges. This report demonstrated functional wide IO memory to 28 nm logic device assembly using 3D package architecture with such a thin form factor.

• Journal of Power Electronics
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• v.15 no.2
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• pp.309-318
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• 2015

This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current-direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an $85-265V_{rms}$ universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.

• Journal of Power Electronics
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• v.19 no.5
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• pp.1203-1215
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• 2019

Sensorless brushless DC (BLDC) motor drive systems are often subjected to inaccurate commutation signals and can produce high current peaks and conduction consumption. To achieve accurate commutation, a fast commutation shift regulation method for sensorless BLDC motor drive systems considering the influence of the inductance freewheeling process is presented to compensate inaccurate commutation signals. The regulation method is effective in both steady speed and variable speed operations. In the proposed method, the commutation error is gained from the line-voltage difference integral in a 60 electrical-degree conduction period and the outgoing phase current before commutation. In addition, the detection precision of the commutation error is improved due to the consideration of the freewheeling period. The commutation error is directly obtained, which avoids successive optimization and accelerates the convergence rate of the proposed method. Moreover, the commutation error features a positive or negative sign, which can be utilized as an indicator of advanced or delayed commutation. Finally, experiments are conducted to validate the effectiveness and feasibility of the proposed method. The results obtained show that the proposed method can accurately regulate commutation signals.