• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1013-1016
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• 1998

A method for generation of design verification tests from behavior-level VHDL program is presented. Behavioral VHDL programs contain multiple communicating processes, signal assignment statements. So for large, complex system, it is difficult problem to test or simulation. In this paper, we proposed a new hardware design verification method. For this method generates control flow graph(CFG.) and process modeling graph(PMG) in the given under the testing VHDL program. And this method proved very effective that all the assumed design errors could be detected.

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2758-2760
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• 1999

ASIC chip design for motor control has been a subject of increasing interest since effective system-on-a-chip design methodology was developed. This paper investigates the design and implementation of ASIC chip for speed control of induction motor using VHDL which is a standarded hardware description language. The presented system is implemented using a simple electronic circuit based on FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.416-419
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• 2015

In this paper, we propose an effective design of transform hardware for real-time HEVC(High Efficiency Video Coding) encoder. HEVC encoder determines the transform mode($4{\times}4$, $8{\times}8$, $16{\times}16$, $32{\times}32$) by comparing RDCost. RDCost require a significant amount of computation and time because it is determined by bit-rate and distortion which is computated via transform, quantization, dequantization, and inverse transform. This paper therefore proposes a new method for transform mode determination using sum of transform coefficient. Also, proposed hardware architecture is implemented with multiplexer, recursive adder/subtracter, and shifter only to derive reduction of the computation. Proposed method for transform mode determination results in an increase of 0.096 in BD-PSNR, 0.057 in BD-Bitrate, and decrease of 9.3% in encoding time by comparing HM 10.0. The hardware which is proposed is implemented by 256K logic gates in TSMC 130nm process. Its maximum operation frequency is 200MHz. At 140MHz, the proposed hardware can support 4K Ultra HD video encoding at 60fps in real time.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.11
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• pp.663-674
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• 2003

Bump mapping is a technique that represents the detailed parts of the object surface, such as a perturberance of the skin of a peanut, using the geometry mapping without complex modeling. However, the hardware implementation for bump mapping is considerable, because a large amount of per pixel computation, including the normal vector shading, is required. In this paper, we propose a new bump mapping algorithm using the polar coordinate system and its hardware architecture. Compared with other existing architectures, our approach performs bump mapping effectively by using a new vector rotation method for transformation into the reference space and minimizing illumination calculation. Consequently, our proposed architecture reduces a large amount of computation and hardware requirements.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.5
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• pp.719-725
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• 1986

Reed-solomon(R-S) code is very effective to coerrect both random and burst errors over a noise communication channel. However, the required hardware is very complex if the B/M algorithm was employed. Moreover, when the error correction system consists of two R-S decoder and de-interleave, the I/O data bns lines becomes 9bits because of an erasure flag bit. Thus, it increases the complexity of hardware. This paper describes the R-S decoder which consisits of a error correction section that uses a direct decoding algorithm and erasure generation section and a erasure generation section which does not use the erasure flag bit. It can be shown that the proposed R-S dicoder is very effective in reducing the size of required hardware for error correction.

• 한국HCI학회:학술대회논문집
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• 2009.02a
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• pp.245-252
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• 2009

We present a design for personalisation of a chording keyboard. There are two primary design goals. Firstly, the keyboard layout should be easy to learn, and easy to use, taking into account the background and physical constraints of the user. Secondly, the keyboard layout should be readily extensible, based on the previous behaviour of the keyboard user. The design proposal accomplishes these goals, and can be simply implemented on cost-effective hardware. In addition, we present preliminary experimental results on optimising the initial keyboard layout.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.415-415
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• 2006

• Proceedings of the KIEE Conference
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• 1999.07f
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• pp.2475-2477
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• 1999

This paper describes a simulation model and scaled hardware model to analyze the dynamic performance of Unified Power Flow Controller, which adjust flexibly the active and reactive power flow through the ac transmission line. The design of control system was developed using vector control method. The results of simulation and scaled hardware test show that the developed control system works accurately. And both models are very effective to analyze the dynamic performance of the Unified Power Flow Controller.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.10
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• pp.579-586
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• 1999

This paper describes a simulation model and a scaled hardware model to analyze the dynamic performance of Unified Power Flow Controller, which can flexibly adjust the active power flow through the ac transmission line. The design of control system for UPFC was developed using vector control method. The results of simulation and scaled hardware test show that the developed control system works accurately. Both models would be very effective for analyzing the dynamic performance of the Unified Power Flow Controller.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.6
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• pp.361-367
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• 2011

In this paper, we propose an interactive embedded system framework for efficient training management in u-health environment. First, we analyzed various requirements of smart training systems for quality of life. We also analyzed the oversea trends and positive effects of the embedded system in terms of both technical and economical factors. Second, we proposed detailed design specification for embedded hardware implementation. Third, we developed effective OS(Operating System) specification for the embedded hardware. Finally, we developed a training scenario and embedded applications such as training control software and analysis software for the smart training systems.