• Journal of KIISE:Computer Systems and Theory
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• v.27 no.3
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• pp.277-286
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• 2000

Switch-based network is suitable for the environment of demanding high performance network. Traditional shared-medium Local Area Networks(LANs) do not provide sufficient throughput and latency. Specially, communication performance is more important with multimedia application. In these environments, switch-based network results in high performance. A kind of switch-based network provides higher bandwidth and low latency. Thus high-speed switch is essential to build switch-based LANs. An effective switch design is the most important factor of the switch-based network performance, and is required for the multicast message processing. In the previous cut-through switching technique, switch element reconfiguration has the capability of multicasting and deadlock-free. However, it has problems of low throughput as well as large scale of switch. Therfore, effective multicating can be implemented by using divided hardware unicast and multicast. The objective of this thesis is to suggest switch configuration with these features.

• The Journal of Korean Association of Computer Education
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• v.6 no.4
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• pp.71-83
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• 2003

This study is aimed to develop and evaluate different approaches for cyber education. The project involved the development of sample cyber education programs using different design approaches, with built-in evaluation mechanisms. The different design approaches depend on what delivery technologies are involved. In the First Generation, the delivery technologies use text, flash and animation, whereas the synchronized content to video and audio are used in the Second and the Third Generations but the difference is the delivery method used by the videoclip. Tests were carried out through self-assessment to measure and analyze the efficient teaching. The results show that the Third generation technologies were the most effective method for cyber education. However, since the Third generation program is developed in multimedia, it tends 10 require higher development costs, and more advanced hardware and software as well as a higher bandwidth for network. Therefore, the research indicates that the development of technical supports, like loading speed, has to be solved simultaneously with the development of multimedia products for effective cyber education.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.364-370
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• 2002

A banknote counter is a machine that automates counting the money in some agencies to treat much banknotes as well as general banking agencies. The banknote counter materialized in this paper is the machine that adds the function of banknote sorting, detecting plural banknote and detecting counterfeit banknote to an existing banknote counter. The technique of sensor signal processing are used for banknote sorting. The technique of sensor application and data processing are used for detecting counterfeit banknote. The technique of precision equipment design and microprocessor application are used for high speed count. Software improved in debugging and difficulties to link with additional hardware. It was materialized through effective control algorithm and real-time signal processing with C-language on the basis of RTOS(real-time operating system) Photodiode, its applications and a magnetic resistance sensor are used as a sensor device with regard to hardware cost -cutting and process velocity. PCF80C552-24 of Philips using Intel I8051 core is used as a control microprocessor. As the results so far achieved, counterfeit banknotes made by the use of a color duplicator and a color Printer, are distinguished from real banknotes through mixing an optical with a magnetic sensor. and, in case that there are some different banknotes while counting, it is prevented for them to be counted without discriminating from the same kind of banknotes in addition to the fu notion of banknote sorting.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• Journal of Korea Multimedia Society
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• v.9 no.7
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• pp.894-903
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• 2006

Rapid technology growth of hardware have brought about development and expansion of various digital motion pictured information including 3-Dimension. 3D digital techniques can be used to be diversity in Animation, Virtual-Reality, Movie, Advertisement, Game and so on. 3D characters in digital motion picture take charge of the core as to communicate emotions and information to users through sounds, facial expression and characteristic motions. Concerns about 3D motion and facial expression is getting higher with extension of frequency in use and range about 3D character design. In this study, the facial expression can be used as a effective method about implicit emotions will be studied and research 3D character's facial expressions and muscles movement which are based on human anatomy and then try to find effective method of facial expression. Finally, also, study the difference and distinguishing between 2D and 3D character through the preceding study what I have researched before.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.3 s.345
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• pp.40-47
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• 2006

The finite-field multiplication can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field multiplication takes much time to compute. In this paper, we propose a radix-4 systolic multiplier on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed standard-basis multiplier is mathematically developed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for VLSI design. Compared to the bit-parallel, bit-serial and systolic multipliers, the proposed multiplier has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field multiplier using Hynix $0.35{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of Korean Society of Steel Construction
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• v.19 no.1
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• pp.15-27
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• 2007

Over the past decade, labor costs have increased relative to the cost of material hardware according to analysts in the construction industry. Therefore, the minimum weight design, which has been widely adopted in the literature for the optimal design of steel structures, is no longer the most economical construction approach. Presently, although connection- related costs is crucial in determining the most cost-effective steel structures, most studies on this subject focused on minimum-weight design or engaged in higher analysis. Therefore, in this study, we proposed a fabrication scheme for the most cost-effective moment-resisting steel frame structures that resist lateral loads without compromising overall stability. The proposed approach considers the cost of steel products, fabrication, and connections within the design process. The optimal design considered construction realities, with the optimal trade-off between the number of moment connections and total cost was achieved by reducing the number of moment connections and rearranging them using the combination of analysis that includes shear, displacement and interaction value based on the LRFD code and optimization scheme based on genetic algorithms. In this study, we have shown the applicability and efficiency in the examples that considered actual loading conditions.

• The Journal of the Korea Contents Association
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• v.17 no.3
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• pp.222-230
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• 2017

The Ministry of Public Safety and Security plans to expand fire safety education infrastructure to provide customized fire safety education, spread fire safety culture and develop a tailored fire safety education system as a part of the 2016 Citizens' Safety Improvement Policy. This study has also been designed to improve safety problems in the Republic of Korea. Even though safety education has been given, citizens aren't still able to experience a close-to-real situation. In addition, their understanding and satisfaction with the curriculum are very low. Therefore, this study offers VR fire-extinguishing experience education contents as an effective alternative. With a goal of having the participants experience fire extinguishing and evacuation drill in a virtual space, this program has the following advantages: i) safe fire-extinguishing experience; ii) UI to create fun ; iii) useful in fire-extinguishing education; iv) budget saving. we configure the VR fire experience system structure and hardware by applying UX design methodology. We also develop for VR-specific motion recognition plug-in and controller that can be feeling in HMD environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.3 s.357
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• pp.35-42
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• 2007

The finite-field division can be applied to the elliptic curve cryptosystems. However, an efficient algorithm and the hardware design are required since the finite-field division takes much time to compute. In this paper, we propose a radix-4 systolic divider on $GF(2^m)$ with comparative area and performance. The algorithm of the proposed divide, is mathematically developed and new counter structure is proposed to map on low-cost systolic cells, so that the proposed systolic architecture is suitable for YLSI design. Compared to the bit-parallel, bit-serial and digit-serial dividers, the proposed divider has relatively effective high performance and low cost. We design and synthesis $GF(2^{193})$ finite-field divider using Dongbuanam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 400MHz.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.