• Title/Summary/Keyword: EEPROM

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High-speed charge pump circuits using weighted-capacitor and multi-path (Weighted-capacitor와 multi-path를 이용한 고속 승압 회로)

  • 김동환;오원석;권덕기;이광엽;박종태;유종근
    • Proceedings of the IEEK Conference
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    • 1998.06a
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    • pp.863-866
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    • 1998
  • In this paper two quick boosting charge pump circuits for high-speed EEPROM memory are proposed. In order to improve initial charge transfer efficiency, one uses weighted capacitors where each stage has different clock coupling capacitance, and the other uses a multi-path structure at the first stage. SPICE simulation results show that these charge pumps have improve drising-time characteristics, but their $V_{DD}$ mean currents are increased a little compared with conventioanl charge pumps. The rising time upt o 15V of the proposed charge pumps is 3 times faster than that of dickson's pump at the cost of 1.5 tiems more $V_{DD}$ mean current.rrent.

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IC 카드를 이용한 신분확인기술연구

  • Gang, Sin-Gak;Kim, Yeong-Hui;Jin, Byeong-Mun
    • ETRI Journal
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    • v.14 no.4
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    • pp.179-193
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    • 1992
  • 반도체 기술의 발전에 힘입어 종래의 자기 카드를 대체할 수 있는 지능형 카드로서 CPU, 메모리 등을 내장하고 있는 IC 카드가 국제표준으로 확정되어 다양한 응용에 적용되고 있다. IC 카드는 연산 및 정보저장 능력뿐만 아니라 외부로부터의 엑세스에 대한 보호능력도 보유하고 있어 다양한 응용분야중에서도 정보보호 시스팀 구성시 중요한 도구로서 각광받고 있다. 본 논문에서는 먼저 IC 카드의 특성 및 현황에 대해 살펴보고, IC 카드를 이용한 신분확인 방식에 대해 살펴보았다. 그리고, 정보보호 기술 중 사용자 및 엔티티간 신분확인 기술에 IC 카드를 적용하여 구현한 내용에 대해 기술하고 있다. IC 카드로는 CPU 와 사용자 공간으로 2KB EEPROM, 그리고 미연방정부 암호 알고리듬 표준인 DES가 내장되어 있는 제품을 사용하였고, 신분확인 알고리듬은 국제표준으로 제정되고 있는 ISO/IEC 9798의 내용중 대칭키 방식을 이용한 신분확인 방식으로, 신뢰할 수 있는 제3자를 통해 신분확인 과정에서 세션키를 제공받는 방식 III를 따라 구현하였다.

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?Color STN (CSTN) LCD Driver Integrated Circuit with Sense Amplifier of Non-Volatile Memory

  • Shin, Chang-Hee;Cho, Ki-Seok;Lee, Yong-Sup;Lee, Jae-Hoon;Sohn, Ki-Sung;Kwon, Oh-Kyong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.6 no.2
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    • pp.87-89
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    • 2006
  • This paper proposes a sense amplifier with non-volatile memory in order to improve the image quality of LCD by enhancing the matching of the driving voltages between the panel and driver. The sense amplifier having a wide sensing margin and fast response adjusts LCD driver voltage of display driver. The CSTN-LCD with the sense amplifier results improved image quality than that with conventional 6 bit column driver without it.

The Design and Implementation of a TV Tuner for the Digital Terrestrial Broadcasting

  • Chong, Young-Jun;Kim, Jae-Young;Lee, Il-Kyoo;Choi, Jae-Ick;Oh, Seung-Hyeub
    • Journal of electromagnetic engineering and science
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    • v.1 no.2
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    • pp.131-138
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    • 2001
  • The DTV (Digital TV) tuner for an 8-VSB (Vestigial Side-Band) modulation was developed to meet the requirements of the ATSC (Advanced Television Systems Committee). The double frequency conversion and the active tracking filter in the front-end were used to cancel interferences between adjacent channels and multi-channels by suppressing the IF beat and the Image frequency. However, It was impossible to get frequency mapping between the tracking filter and the first VCO (Voltage Controlled Oscillator) in the existing DTV tuner structure which differs from the NTSC (National Television Systems Committee) tuner. This paper, therefore, suggests an assailable structure and a new method for the automatic frequency selection by mapping the frequency characteristics over the tracking voltage and the combined HW which is composed of a Micro-controller, an EEPROM (Electrically Erasable Programmable Read Only Memory), a DAC (Digital-to-Analog Converter), an OP amplifier, and a switch driver.

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Design of a Full-Duplex RFID chip with Demodulator (Demodulator를 탑재한 Full-Duplex RFID칩 설계)

  • Kim, Do-Gyun;Lee, Kwang-Youb
    • Proceedings of the Korea Information Processing Society Conference
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    • 2000.10a
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    • pp.465-468
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    • 2000
  • 본 논문에서는 인식코드를 전송할 수 있는 modulator 뿐만 아니라 Reader system으로부터 코드 전송제어 명령어를 수신할 수 있고 향후 EEPROM과 더불어 인식코드를 수정할 수 있는 RFID (Radio Frequency IDentification) Transponder 칩 설계에 관한 내용을 다룬다. RFID칩은 배터리를 사용하지 않고 명령어와 함께 형성되는 Field로부터 전원을 생성하고 동시에 코드를 제공하는 Full-Duplex 구조로 설계하였다. Transponder IC는 power-generation 회로, clock generation 회로, digital block, modulator, overvoltage protection 회로로 구성된다. 설계된 칩은 저전력 회로를 적용하여 원거리 transponder칩을 구현할 수 있도록 하였다. 설계된 회로는 $0.6{\mu}m$ 현대 CMOS 공정으로 레이아웃 하였으며 제작중에 있다.

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Development of switching control circuit for blinking operation of fluorescent lamps (형광램프의 점멸동작을 위한 스위칭 제어회로의 개발)

  • Song, Sang-Bin;Jeong, Young-Hoon;Gwark, Jae-Young;Yeo, In-Seon
    • Proceedings of the KIEE Conference
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    • 1999.11b
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    • pp.352-354
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    • 1999
  • A Switching control circuit based on a micro-controller is developed for blinking operation of fluorescent lamps, which would be suitable for use in the advertising panel. Ten modes of blinking patterns are implanted within the EEPROM. The developed circuit can handle up to 128 fluorescent lamps of 20-40W range, and the lamp life is expected to so beyond 3000 hours.

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Embedded System for Automatic Condensation Control of the Car

  • Lee, Dmitriy;Bae, Yong-Wook;Lee, Neung-Ho;Seo, Hee-Don
    • Journal of Sensor Science and Technology
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    • v.21 no.1
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    • pp.21-27
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    • 2012
  • In this study, we designed an embedded system for automatic condensation control(ESCC) of the car. This system heats the car glasses as and when it is needed that makes driving safer and convenient. The system was built on an ATmega128L central processing unit(CPU), using high-performance electrically erasable programmable read-only memory(EEPROM) complex programmable logic device(CPLD) ATF1504AS, using which an ESCC algorithm has been proposed. The source code was written in C language. The algorithm of work was written using the dew-point table. This system not only clears the condensation on the glass but also averts condensation. The designed ESCC system begins working once the input information comes close to the dew-point table information. This device enables a wider field of view, thereby increasing safety.

A Study on the Characteristics of Synaptic Multiplication for SONOSFET Memory Devices (SONOSFET 기억소자의 시랩스 승적특성에 관한 연구)

  • 이성배;김병철;김주연;이상배;서광열
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1996.11a
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    • pp.1-4
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    • 1996
  • EEPROM technology has been used for storing analog weights as charge in a nitride layer between gate and channel of a field effect transistor. In the view of integrity and fabrication process, it is essentially required that SONOSFET is capable of performing synapse function as a basic element in an artificial neural networks. This work has introduced the VLSI implementation for synapses including current study and also investigated physical characteristics to implement synapse circuit using SONOSFET memories. Simulation results are shown in this work. It is proposed that multiplication of synapse element using SONOSFET memories will be developed more compact implementation under Present fabrication processes.

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Impact of LDD Structure on Single-Poly EEPROM Characteristics

  • Na, Kee-Yeol;Park, Mun-Woo;Kim, Kyung-Hoon;Kim, Nan-Soo;Kim, Yeong-Seuk
    • Journal of Electrical Engineering and information Science
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    • v.3 no.3
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    • pp.391-395
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    • 1998
  • The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-poly EEPROMs are fabricated using the 0.8$\mu\textrm{m}$ CMOS ASIC process. The single-poly EEPROMs with LDD structure have slower program and erase speeds, but the drain and gate stresses and the endurance characteristics of these devices are much better than those of the single-poly EEPROMs with single-drain structure. The single-poly EEPROMs with LDD structure do not require the process modifications and need no additional masks, hence can be used for microprocessors and logic circuits with low-density and low-cost embedded EEPROMs.

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A Study on the Low Level Leakage Currents of Silicon Oxides (실리콘 산화막의 저레벨 누설전류에 관한 연구)

  • 강창수;김동진
    • Journal of the Korean Institute of Telematics and Electronics T
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    • v.35T no.1
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    • pp.29-32
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    • 1998
  • The low level leakage currents in silicon oxides were investigated. The low level leakage currents were composed of a transient component and a do component. The transient component was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The do component was caused by trap assisted tunneling completely through the oxide. The low level leakage current was proportional to the number of traps generated in the oxides. The low level leakage current may be a trap charging and discharging current. The low level leakage current will affect data retention in EEPROM.

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