• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.12 no.5
• /
• pp.15-25
• /
• 2002

In this paper a design of high performance cryptographic processor which implements AES Rijndael algorithm is described. To eliminate performance degradation due to round-key computation delay of conventional processor, the on-the-fly precomputation of round key based on modified round structure is adopted. And on-the-fly round key generator which supports 128, 192, and 256-bit key has modular structure. The designed processor has iterative structure which uses 1 clock cycle per round and supports three operation modes, such as ECB, CBC, and CTR mode which is a candidate for new AES modes of operation. The cryptographic processor designed in Verilog-HDL and synthesized using 0.251$\mu\textrm{m}$ CMOS cell library consists of about 51,000 gates. Simulation results show that the critical path delay is about 7.5ns and it can operate up to 125Mhz clock frequency at 2.5V supply. Its peak performance is about 1.45Gbps encryption or decryption rate under 128-bit key ECB mode.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.9B
• /
• pp.1609-1617
• /
• 2000

In this paper a design of cryptographic coprocessor which implements SEED algorithm is described. To satisfy trade-off between area and speed, the coprocessor has structure in which 1 round operation is divided into three subrounds and then subround is executed for one clock. To improve clock frequency online precomputation scheme for round key is used. To apply the coprocessor to various applications, four operating modes such as ECB, CBC, CFB, and OFB are supported. Also to eliminate performance degradation due to data input and data output time between host computer and coprocesor, background input/output method is used. The cryptographic coprocessor is designed using $0.25{\mu}{\textrm}{m}$ CMOS technology and consists of about 29,300 gates. Its peak performance is about 237 Mbps encryption or decryption rate under 100 Mhz clock frequncy and ECB mode.

• Proceedings of the Korean Information Science Society Conference
• /
• 1999.10c
• /
• pp.285-287
• /
• 1999

블록 암호알고리즘에 대한 기존의 연산 모드들(ECB 또는 CBC 등)은, 각 블록에 대하여 동일한 키로 암호화를 수행한다. 이것은 침입자가 한번의 암호 요청만을 수행하여 많은 수의 평문/암호문 쌍을 얻을 수 있게 함으로써 차분해독법 등의 공격에는 안전성을 제공하지 않는다. 본 논문에서는 블록 암호 알고리즘을 위한 새로운 모드를 제안하는데, 이 모드에서는 암호화되는 각각의 블록이 서로 다른 키로 암호화되도록 함으로써 블록의 개수가 많아짐에 따라 안전성 면에서 상당한 이득을 얻게 된다. 각 블록을 위한 서로 다른 키를 생성하는 것이 추가 연산을 필요로 하지만, 제안하는 모드를 DES에 적용한 TDK(a mode for DEA with unTraceable Dynamic Keys)의 수행 시간을 pentium과 sun sparc 상에서 측정해 본 결과 ECB 모드와 거의 유사함을 알 수 있었다.

• KIPS Transactions on Computer and Communication Systems
• /
• v.11 no.6
• /
• pp.167-174
• /
• 2022

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.6
• /
• pp.1163-1170
• /
• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2004.05a
• /
• pp.206-209
• /
• 2004

We investigated response characteristics of liquid crystal display(LCD) with different operating mode of nematic liquid crystals (NLCs) such as $45^{\circ}$twist nematic (TN), $67.3^{\circ}$TN and ECB(electrical controlled birefringence) on a rubbed polyimide (PI) surface. The three kinds of LCD operating mode obtain stable EO performance. Low transmittances of the $45^{\circ}$TN and $67.3^{\circ}$TN cell on the rubbed PI surface were achieved by using low cell gap d. The fast response time of ECB cell among the three kinds of LCD operating mode was measured.

• Proceedings of the KIEE Conference
• /
• 2015.07a
• /
• pp.1603-1604
• /
• 2015

ECB(Eddy Current Brake)는 철도시스템의 고속에서 제동력을 안정적으로 나타낼 수 있어서 TGV, ICE, JR-500등과 같은 철도에서 사용되고 있다. 하지만 저속에서는 효율적이지 못하고, 전자석은 경량성에 대한 문제와 에너지를 소비한다는 단점을 가지고 있다. 이 논문에서는 제안된 영구자석형 Shield moving형 와전류 제동기를 사용하였다. 이 와전류 제동기는 Shield의 각을 이동하여 제동력을 조절할 수 있으며 영구자석을 이용함으로서 전자석의 단점을 보안하였다. 하지만 영구자석은 온도에 대해 영향을 받을 수 있으므로 온도 특성은 전류밀도(J(A/m2))와 자속밀도(T)를 'Ansoft Maxell'을 시뮬레이션하여 확인하였다.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.51 no.12
• /
• pp.659-663
• /
• 2002

The brake systems of high-speed train are to be equipped with three different brake systems, such as regenerative brake with regenerative feedback in driving car, a pneumatic disc brake, and non-contact linear eddy-current brake(ECB). The regenerative brake and the pneumatic disc brake are acting on the wheels. Their achievable braking force depends on the adhesive coefficient, which is influenced by the weather condition and speed, between the wheel and The linear eddy current brake gets an economical solution in the high-speed train because of the independence of the adhesive coefficient, no maintenance needed. and the good control characteristics. The braking force and the normal force of ECB for korean high-speed train are analysed by the 2D FEM(Finite Element Method). Finally the normal force is compared with the experiential values to verify the analysis.

• Journal of KIISE:Information Networking
• /
• v.29 no.2
• /
• pp.156-164
• /
• 2002

IPSec is a protocol which provides data encryption, message authentication and data integrity on public and open network transmission. In IPSec, ESP protocol is used when it needs to provide data encryption, authentication and Integrity In real transmission packets. ESP protocol uses DES-CBC encryption mode when sender encrypts packets and receiver decrypts data through this mode IV is used at that time. This value has many tasks of attack during transmission by attacker because it is transferred clean and opened. If IV value is modified, then decryption of ESP data is impossible and higher level information is changed. In this paper we propose a new algorithm that it encrypts IV values using DES-ECB mode for preventing IV attack and checks integrity of whole ESP data using message authentication function. Therefore, we will protect attacks of IV and data, and guarantee core safe transmission on the public network.

• The KIPS Transactions:PartC
• /
• v.9C no.2
• /
• pp.189-196
• /
• 2002

IPSec is a protocol which provides data encryption, message authentication and data integrity on public and open network transmission. In IPSec, ESP protocol is used when it needs to Provide data encryption, authentication and integrity in real transmission Packets. ESP protocol uses DES-CBC encryption mode when sender encrypts packets and receiver decrypts data through this mode IV is used at that tome. This vague has many risks of attack during transmission by attacker because it is transferred clean and opened. If IV value is modified, then decryption of ESP data is impossible and higher level information is changed. In this paper we propose a new algorithm that it encrpty IV values using DES-ECB mode for preventing IV attack and checks integrity of whole ESP data using message authentication function. Therefore, we will protect attacks of IV and data, and guarantee more safe transmission on the public network.