• Journal of KIISE:Computing Practices and Letters
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• v.16 no.11
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• pp.1051-1055
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• 2010

Software defined radio(SDR) technology implements wireless communication protocols as software instead of dedicated hardware. SDR enables reconfiguration of wireless communication protocols without expensive hardware modification. However, as the SDR systems are equipped with additional programmable processors, they suffer significant power dissipation. This paper proposes a novel power management technique for SDR systems, called the combined modulation and voltage scaling (CMVS). Numerical analyses were performed to evaluate the effectiveness of CMVS. The results show that CMVS minimizes power dissipation while satisfying the given data transfer rate.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.22-28
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• 2009

As multiprocessors have been widely adopted in embedded systems, task computation energy consumption should be minimized with several low power techniques supported by the multiprocessors. This paper proposes an energy-aware task scheduling algorithm that adopts both dynamic voltage scaling and power shutdown in multiprocessor environments. Considering the timing and energy overhead of power shutdown, the proposed algorithm performs an iterative task assignment and task ordering for multiprocessor systems. In this case, the iterative priority-based task scheduling is adopted to obtain the best solution with the minimized total energy consumption. Total energy consumption is calculated by considering a linear programming model and threshold time of power shutdown. By analyzing experimental results for standard task graphs based on real applications, the resource and timing limitations were analyzed to maximize energy savings. Considering the experimental results, the proposed energy-aware task scheduling provided meaningful performance enhancements over the existing priority-based task scheduling approaches.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.5
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• pp.866-874
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• 2006

This paper proposes a new Dynamic Voltage Scaling(DVS) algorithm to achieve low-power scheduling of aperiodic hard real-time tasks. Aperiodic tasks schedulingcannot be applied to the conventional DVS algorithm and result in consuming energy more than periodic tasks because they have no period, non predictable worst case execution time, and release time. In this paper, we defined Virtual Periodic Task Set(VTS) which has constant period and worst case execution time, and released aperiodic tasks are assigned to this VTS. The period and worst case execution time of the virtual task can be obtained by calculating task utilization rate of both periodic and aperiodic tasks. The proposed DVS algorithm scales the frequency of both periodic and aperiodic tasks in VTS. Simulation results show that the energy consumption of the proposed algorithm is reduced by 11% over the conventional DVS algorithm for only periodic task.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.279-281
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• 2006

In this paper, we study an approach to design a self-tuning Fuzzy-PI controller in HVDC(High Voltage Direct Current) system. In the rectifier of conversional HVDC system, turning on, turning off, triggering and protections of thyristors have lots of problems that can make the dynamic instability and cannot damp the dynamic disturbance efficiently. The above problems are solved by adapting Fuzzy-PI controller for the fire angle control of rectifier.[7] The performance of the Fuzzy-PI controller is sensitive to the variety of scaling factors. The design procedure dwells on the use of evolutionary computing(Genetic Algorithms, GAs). Then we can obtain the optimal scaling factors of the Fuzzy-PI controller by Genetic Algorithms. In order to improve Fuzzy-PI controller, we adopt FIS to tune the scaling factors of the Fuzzy-PI controller on line. A comparative study has been performed between Fuzzy-PI and self-tuning Fuzzy-PI controller, to prove the superiority of the proposed scheme.

• Journal of Korea Multimedia Society
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• v.13 no.1
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• pp.30-37
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• 2010

Many embedded real - lime systems have adopted processors supported with dynamic voltage scal-ing(DVS) recently. Power is one of the important metrics for Optimization in the design and operation of embedded real-time systems. We can save considerable energy by using slowdown of processor sup-ported with DVS. In this paper, we improved the previous algorithm at a point of view of time complexity to calculate task slowdown factors for an efficient energy consumption in embedded real-time systems with task synchronization. We grasped the properties of the previous algorithm having $O(n^{2})$ time complexity through mathematical analysis and s simulation. Using its properties we proposed the improved algorithms with O(nlogn) and O(n) time complexity which have the same performance as the previous algorithm has.

• Journal of KIISE:Computer Systems and Theory
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• v.35 no.6
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• pp.273-283
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• 2008

Many embedded real-time systems have adopted processors supported with dynamic voltage scaling(DVS) recently. Power is one of the important metrics for optimization in the design and operation of embedded real-time systems. We can save considerable energy by using slowdown of processor supported with DVS. In this paper, we propose heuristic algorithms to calculate task slowdown factors for an efficient energy consumption in embedded real-time systems with task synchronization. The previous algorithm has a following constraint : given the tasks are ordered in a nondecreasing order of their relative deadline, the task slowdown factors computed are in a nonincreasing order. In this paper, we relax the constraint and propose heuristic algorithms which have the same time complexity that previous algorithm has and can save more energy. Experimental results show that the proposed algorithms are energy efficient.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.10
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• pp.543-552
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• 2004

This paper proposes an energy optimization technique for latency and quality constrained video applications. It consists of two key techniques: frame-skipping technique and buffering technique. While buffering increases the slack time utilization at the OS level. frame skipping Increases the slack time itself at the application level, and both enhance the effectiveness of the dynamic voltage scaling technique. We use an H.263 encoder application as a test vehicle to which the proposed technique is applied. Experiments demonstrate that the proposed technique achieves noticeable energy reduction satisfying the given latency and video quality constraints.

• Journal of Satellite, Information and Communications
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• v.8 no.3
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• pp.10-14
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• 2013

In this paper, when applying current-mode circuit design technique showing constant power dissipation none the less operation frequency, to the low power design of dynamic voltage frequency scaling, we introduce the low power current-mode circuit design technique applying MOSFET in sub-threshold region, in order to solve the problem that has large power dissipation especially on the condition of low operating frequency. BSIM 3, was used as a MOSFET model in circuit simulation. From the simulation result, the power dissipation of the current memory circuit with sub-threshold MOSFET showed $18.98{\mu}W$, which means the consumption reduction effect of 98%, compared with $900{\mu}W$ in that with strong inversion. It is confirmed that the proposed circuit design technique will be available in DVFS using a current-mode circuit design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9B
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• pp.1082-1091
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• 2011

Power-reduction techniques based on DVFS(Dynamic Voltage and Frequency Scaling) are crucial for lengthening operating times of battery powered mobile systems. This paper proposes an optimal DVFS scheduling algorithm for decoders with memory size limitation on display buffer, which is realistic constraints not properly touched in the previous works. Furthermore, we mathematically prove that the proposed algorithm is optimal in the limited display buffer and limited clock frequency model, and also can be used for feasibility check. Simulation results show the proposed algorithm outperformed the previous heuristic algorithms by 7% in average, and the performance of all algorithms using display buffers saturates at about 10 frame size.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.30 no.3
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• pp.1-8
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• 2016

In this paper, we proposed a new driving scheme to reduce the motion blur and save the power for OLEDs(organic light emitting diodes). We adopted a DVS (dynamic voltage scaling) method to reduce power consumption and the division of TV field to improve motion blur. In the proposed scheme, BEW (Blur Edge Width) was decreased to the ratio of 1/4 compared to the conventional scheme under the optimal conditions. In this scheme, the gray levels to which the DVS method can be applied were divided into much smaller groups depending on the number of subfields. Therefore, our scheme does not guarantee less power consumption for every image compared to the conventional scheme. However, the new scheme can move the gray levels adopting the DVS to higher gray levels. Thus, we can save power even when having images at high gray levels.