• 제목/요약/키워드: Dynamic Addressing

검색결과 77건 처리시간 0.042초

Enhanced DCDP를 이용한 MANET에서의 Dynamic Addressing Technique (Dynamic Addressing Technique in MANET Using an Enhanced DCDP)

  • 나상준;이수경;송주석
    • 한국정보과학회:학술대회논문집
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    • 한국정보과학회 2004년도 가을 학술발표논문집 Vol.31 No.2 (3)
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    • pp.709-711
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    • 2004
  • 네트워크에서의 IP address는 통신을 하기 위한 가장 중요한 요소라고 할 수 있다. 네트워크 상에 존재하는 모든 node들은 자신의 IP address를 가지고 나서야 통신에 참여할 수 있다. 최근 MANET에서의 라우팅 프로토콜에 대한 많은 연구가 진행되고 있으며, 이와 함께 dynamic addressing technique에 대한 연구도 활발히 이루어지고 있다. 본 논문에서는 여러 가지 방식의 dynamic addressing technique들 중에서 빠르고 효율적인 Dynamic Configuration and Distribution Protocol (DCDP)에 대해 살펴보고 보다 안정적인 address 할당 기술을 이용한 Enhanced DCDP를 제안한다.

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Hop-by-Hop Dynamic Addressing Based Routing Protocol for Monitoring of long range Underwater Pipeline

  • Abbas, Muhammad Zahid;Bakar, Kamalrulnizam Abu;Ayaz, Muhammad;Mohamed, Mohammad Hafiz;Tariq, Moeenuddin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제11권2호
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    • pp.731-763
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    • 2017
  • In Underwater Linear Sensor Networks (UW-LSN) routing process, nodes without proper address make it difficult to determine relative sensor details specially the position of the node. In addition, it effects to determine the exact leakage position with minimized delay for long range underwater pipeline monitoring. Several studies have been made to overcome the mentioned issues. However, little attention has been given to minimize communication delay using dynamic addressing schemes. This paper presents the novel solution called Hop-by-Hop Dynamic Addressing based Routing Protocol for Pipeline Monitoring (H2-DARP-PM) to deal with nodes addressing and communication delay. H2-DARP-PM assigns a dynamic hop address to every participating node in an efficient manner. Dynamic addressing mechanism employed by H2-DARP-PM differentiates the heterogeneous types of sensor nodes thereby helping to control the traffic flows between the nodes. The proposed dynamic addressing mechanism provides support in the selection of an appropriate next hop neighbour. Simulation results and analytical model illustrate that H2-DARP-PM addressing support distribution of topology into different ranges of heterogeneous sensors and sinks to mitigate the higher delay issue. One of the distinguishing characteristics of H2-DARP-PM has the capability to operate with a fewer number of sensor nodes deployed for long-range underwater pipeline monitoring.

Influence of wall charge configurations prior to addressing discharge on dynamic margin in AC Plasma Display Panel

  • Jung, Y.;Choi, J.H.;Jung, K.B.;Kim, S.B.;Choi, E.H.
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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    • pp.764-767
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    • 2003
  • We have experimentally investigated the influence of wall charge configurations prior to addressing discharge on dynamic margin in AC plasma display panel. In this experiment, we have analyzed the quantity and polarity of wall charge accumulated on the front and rear dielectrics just prior to the addressing discharge under the conventional driving sequence.

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Autonomous, Scalable, and Resilient Overlay Infrastructure

  • Shami, Khaldoon;Magoni, Damien;Lorenz, Pascal
    • Journal of Communications and Networks
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    • 제8권4호
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    • pp.378-390
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    • 2006
  • Many distributed applications build overlays on top of the Internet. Several unsolved issues at the network layer can explain this trend to implement network services such as multicast, mobility, and security at the application layer. On one hand, overlays creating basic topologies are usually limited in flexibility and scalability. On the other hand, overlays creating complex topologies require some form of application level addressing, routing, and naming mechanisms. Our aim is to design an efficient and robust addressing, routing, and naming infrastructure for these complex overlays. Our only assumption is that they are deployed over the Internet topology. Applications that use our middleware will be relieved from managing their own overlay topologies. Our infrastructure is based on the separation of the naming and the addressing planes and provides a convergence plane for the current heterogeneous Internet environment. To implement this property, we have designed a scalable distributed k-resilient name to address binding system. This paper describes the design of our overlay infrastructure and presents performance results concerning its routing scalability, its path inflation efficiency and its resilience to network dynamics.

Invited Paper: Progresses in BiNem display technology for e-reading applications

  • Angele, Jacques;Joly, Stephane;Martinot-Lagarde, Philippe;Faget, Luc;Osterman, Jesper;Scheffer, Terry;Leblanc, Francois
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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    • pp.83-86
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    • 2009
  • BiNem$^{(R)}$ displays have entered volume manufacturing in 2009. Applications range from e-labels to e-readers. We have developed 6-inch $960{\times}720$ pixels passive matrix BiNem prototypes achieving 40 % brightness and fluid user interface based on partial image / dynamic pointer addressing. Active-matrix addressing is proposed to provide even faster operation.

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New Address Electrode Suitable for Fast Addressing with High Xe ac-PDP

  • Lee, Don-Kyu;Lee, Ho-Jun;Lee, Hae-June;Kim, Dong-Hyun;Park, Chung-Hoo
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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    • pp.564-567
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    • 2004
  • New address electrode having separated dual electrode is suggested to reduce addressing time in ac PDP. Addressing characteristics of suggested electrode has been investigated in the test panel with high Xe partial pressure. It has been found that both the formative and jitter width of the suggested electrode is improved by 10 -20 % over the wide range of address voltage level compared with the conventional one. The dynamic margin of the panel also greatly improved. The key feature behind this type of structure is that it can extend the controllability of the wall charge distribution during the reset and address discharge without significant increase in capacitive load of address electrode.

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임베디드 프로세서의 성능 향상을 위한 DIAM의 진보한 아키텍처 (Advanced Architecture using DIAM for Improved Performance of Embedded Processor)

  • 윤종희;신세철;백윤홍;조정훈
    • 정보처리학회논문지A
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    • 제16A권6호
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    • pp.443-452
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    • 2009
  • 32비트 아키텍처가 현대 마이크로프로세서의 표준이 되어가고 있음에도 불구하고 작은 사이즈와 적은 파워 소모량을 우선시 하는 저가의 프로세서에서는 여전히 16비트 아키텍처가 사용되고 있다. 그러나 16비트 아키텍처는 특정 애플리케이션을 위한 특별한 명령어들을 추가할 만 한 충분한 인코딩 공간이 제공되지 않는 결정적인 단점을 가지고 있다. 이것을 극복하기 위해 기존의 많은 아키텍처에서 일반적이지 않은 다양 한 어드레싱 모드들을 수용하기 위한 직교적이지 않으면서(non-orthogonal) 불규칙한 명령어 셋이 사용되었다. 일반적으로 직교적이지 않은 아 키텍처들은 최적의 코드를 생성하기 위해서 매우 정교한 컴파일러 기술을 요구하는 경향이 있기 때문에 컴파일러에 지향적이지 않는 것으로 간주된다. 이전에 우리는 이런 문제를 해결하기 위해 새로운 어드레싱 모드인 DIAM (dynamic implied addressing mode)을 사용하는 컴파일러 지향적 프로세서를 제안하였다. 이 논문에서는16비트 프로세서에서 우리의 애플리케이션들을 위해 더 많은 인코딩 공간을 제공하였던 DIAM을 사용하는 아키텍처를 설명하고, 그것을 보완하여 성능이 더욱 개선된 아키텍처에 대하여 설명할 것이다. 우리의 실험에서 제안된 아키텍처는 기존의 아키텍처에 비해 평균적인 성능을 11.6% 증가시켰다.

서로 다른 임계압력을 가지는 디지털 밸브가 설치된 제어라인을 이용한 3 진 유체분배기 (A Ternary Microfluidic Multiplexer using Control Lines with Digital Valves of Different Threshold Pressures)

  • 이동우;조영호
    • 대한기계학회논문집A
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    • 제33권6호
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    • pp.568-572
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    • 2009
  • We present a ternary microfluidic multiplexer unit, capable to address three flow channels using a pair of control lines with two different threshold pressure valves. The previous binary multiplexer unit addresses only two flow channels using a pair of control line with identical threshold pressure valves, thus addressing $2^{n/2}$ flow channels using n control lines. The present ternary multiplexer addressing three flow channels using a pair of control lines, however, is capable to address $3^{n/2}$ flow channels using n control lines with two different threshold pressure valves. In the experimental study, we characterized the threshold pressure and the response time of the valves used in the ternary multiplexer. From the experimental observation, we also verified that the present ternary multiplexer unit could be operated by two equivalent valve operating conditions: the different static pressures and dynamic pressures at different duty ratio. And then, $3{\times}3$ well array stacking ternary multiplexers in serial is addressed in cross and plus patterns, thus demonstrating the individual flow channel addressing capability of the ternary multiplexer. Thus, the present ternary multiplexer reduces the number of control lines for addressing flow channels, achieving the high well control efficiency required for simple and compact microfluidic systems.

동영상 의사윤곽 개선을 위한 새로운 ac PDP 계조구현 방법 (New Gray Scale Implementaion Method for Improving Dynamic False Contours in ac PDPs)

  • 정영호;정주영
    • 대한전자공학회논문지SD
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    • 제41권1호
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    • pp.1-8
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    • 2004
  • Quantized memory addressing (QMA) 이론을 바탕으로 새로운 PDP 계조 구현을 수행하는 방법을 개발하였다. 어드레스 펄스 폭을 조절함에 따라 셀에 기입되는 벽전하 양은 "fully on", "off" 그리고 "half on"의 세 단계를 가지게 된다. 이 세 단계의 벽전하를 이용하여 7개의 서브필드로 255단계의 계조를 표현할 수 있다. 더욱이 기존의 구동 방법과는 달리 인접한 두 계조를 표현하기 위해 사용하는 서브필드들이 동영상 의사윤곽을 제거한다. 이 방법은 7개의 서브필드를 사용함으로써 12개의 서브필드를 이용하여 동영상 의사 윤곽을 저감시킨 방법에 비해 유지 방전 시간을 $70\%$이상 증가시킨다.

Address and Display Period Complex Driving for Expanding Gray Scale

  • Jung, Kwang-Sig;Kim, Gop-Sig;Shin, Seung-Rok;Chae, Su-Yong;Kim, Dae-Hwan;Yoo, Min-Sun;Cho, Yoon-Hyoung
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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    • pp.647-650
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    • 2005
  • A new driving scheme, Address and Display Period Complex Driving for Expanding Gray Scale(ACE), is proposed by mixing Address Display period Separated(ADS) and Address While Display(AWD). In this method scan lines are divided in blocks driving by AWD and scan lines in block progress sequential high speed addressing. ADS driving get accomplished in low gray level for expanding gray scale. Scan time is reduced and the number of subfields is increased by high speed addressing of ACE. That expands the gray scale and decreases the dynamic false contour. Also, that improves contrast by using ramp reset.

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