• Journal of international Conference on Electrical Machines and Systems
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• v.3 no.2
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• pp.155-161
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• 2014

Industrial Static Var Generator (SVG) is typically applied at or near the load center to mitigate voltage fluctuation, flicker, phase unbalance, non-sine distortion or other load-related disturbance. Special attention is paid to the influence of grid voltage quality on SVG current, the non-sine distortion and unbalance of grid voltage causes not only the AC current distortion and unbalance but also the DC voltage fluctuation. In order to let the inverter voltage contain the fundamental negative sequence and harmonic component corresponding to the grid voltage, a new dual-loop control scheme is proposed to suppress the influence in this paper. The harmonic and negative sequence voltage decomposition algorithm and DC voltage control are also introduced. All these analyses can guide the practical applications. The simulation results verify the feasibility and effectiveness of the present control strategy and analyses.

• Journal of Korean Society for Quality Management
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• v.28 no.1
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• pp.105-118
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• 2000

In this paper, we consider an interconnection network, DRDT (Dual Receive Dual Transmit), that is a double-loop ring topology and adopts the concept of multiple packets transmission. For three types of DRDT configurations, we investigate some properties related to path sets and discuss the method for finding minimal path sets. Using the concept of the terminal reliability and the path sets approach, we evaluate the reliability of the DRDT networks and compare them with a single ring network and a unidirectional double-loop ring network.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.414-419
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• 1998

This paper describes the dynamical performance of a four-quadrant circulation current mode control of dc motor drive, using the controlled flywleeling technique, a four-quadrant closed-loop control drive with an inner current control loop and a speed fuzzy PI regulator is designed. The obtained computer simulation results of a dc motor drive below and above the base speed are demonstrated. These result show that compare to a conventional dual-converter-fed dc motor drive with simultaneous control, the overal system performance has been improved and also, agood stability and robstness has been achieved.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2057-2066
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• 2016

An extension of the one-cycle control (OCC) method for switched-capacitor (SC) converters is proposed in this paper, featuring a fast dynamic response, wide line and load operation ranges, and simplicity in implementation. To illustrate the operation principle of this nonlinear control method and to demonstrate its simplicity in design, a dual-phase unity gain SC converter is examined. A new control loop based on the charge balance in a flying capacitor is formulated for the OCC technique and implemented with a 15W dual-phase unity gain SC converter on a circuit board for control verification. The obtained experimental results show that external disturbances can be rejected in one switching cycle by the OCC controlled SC converter with good line and load regulations. When compared to other control methods, the proposed nonlinear control loop exhibits superior dynamic performance in suppressing input and load disturbances.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.63-64
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• 2006

In this paper, the open loop antenna using a strip-conductor for an RFID reader at dual-band frequency(910MHz, 2.45GHz) is proposed. The impedance is matched by varying the antenna parameters such as the length of strip-conductor and the gap of between two strip-conductors. Return loss and gain of designed antenna are -11.919dB, 2.5dBi at 910MHz, and -15.766dB, 5.65dBi at 2.45GHz, respectively.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.6
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• pp.543-546
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• 2017

This paper presents a simple approach for improving the performance of back-electromotive force (back-EMF)-estimation-based sensorless drives for surface-mounted permanent magnet synchronous motors (SPMSM). Similar to conventional approaches, a hypothetical d-q synchronous reference frame model of SPMSM is employed in the proposed approach to estimate the back-EMFs. This approach also employs a dual phase locked loop structure to compensate for the effect of the dead time and parameter uncertainty of the inverter on the estimated back-EMFs. The proposed algorithm is validated by conducting experiments.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.4
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• pp.509-518
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• 2014

Though various techniques have been studied as a way of adjusting parameters of PID controllers, no perfect method of determining parameters is available to date. Especially the deign of PID controller for unstable processes with dead time(UPWDT) is even more difficult due to various reasons. Generally the existing design procedures for UPWDT involve deriving formulas to meet gain and phase margin specifications, or using inner loop to stabilize UPWDT before applying PID controller. In this paper, the dual-input describing function(DIDF) method is proposed, by which the performance and robustness of the closed-loop system can be improved. The method is based on moving the critical point (-1+j0) of Nyquist stability to a new position arbitrarily selected on the complex plane. This can be done by determining appropriate coefficients of the DIDF. As a result, we can easily determine parameters of PID-type controller by using existing conventional tuning methods for stable or unstable systems. Simulation results are included to show the effectiveness of the proposed method.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.41-45
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• 2015

In this paper, the single port dual-band resonator for magnetic resonance wireless power transfer is proposed. The proposed dual-band resonator is consists of 20 turns spiral coil, a single loop, matching circuit, lumped elements, and a single port. The two sides of the matching circuit are connected to via holes. The spiral coil is operated at MF-band and single loop is operated at HF-band, respectively. We use two of the same structure resonators and simulated and the power transfer efficiency was calculated. The efficiency of simulation and measurement is above 60% at the MF and HF bands, and the distance is 100 mm.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.10
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• pp.479-485
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• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.