• Title/Summary/Keyword: Dual-Loop

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A dual-loop boost-converter LED driver IC with temperature compensation (온도 보상 및 듀얼 루프를 이용한 부스트 컨버터 LED 드라이버 IC)

  • Park, Ji-Hoon;Yoon, Seong-Jin;Hwang, In-Chul
    • Journal of Korea Society of Industrial Information Systems
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    • v.20 no.6
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    • pp.29-36
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    • 2015
  • This paper presents an LED backlight driver IC consisting of three linear current regulators and an output-voltage regulation loop with a self-adjustable reference voltage. In the proposed LED driver, the output voltage is controlled by dual feedback loops. The first loop senses and controls the output voltage, and the second loop senses the voltage drop of the linear current regulator and adjusts the reference voltage. With these feedback loops, the voltage drop of the linear current regulator is maintained at a minimum value, at which the driver efficiency is maximized. The output of the driver is a three-channel LED setup with four LEDs in each channel. The luminance is adjusted by the PWM dimming signal. The proposed driver is designed by a $0.35-{\mu}m$ 60-V high-voltage process, resulting in an experimental maximum efficiency of approximately 85%.

Compact Dual-band CPW-fed Slot Antenna Using Split-Ring Resonator (분할 링 공진기를 이용한 소형 이중 대역 CPW-급전 슬롯 안테나)

  • Yeo, Junho;Park, Jin-Taek;Lee, Jong-Ig
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.11
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    • pp.2526-2533
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    • 2015
  • In this paper, a design method for a compact dual-band coplanar waveguide-fed slot antenna using SRR(split-ring resonator) conductor is studied. The SRR conductor is loaded inside a rectangular slot of the proposed antenna for dual-band operation. When the SRR conductor is inserted into the slot, the original rectangular slot is divided into a rectangular loop region and a rectangular slot region, and frequency bands are created by the loop and slot, separately. A prototype of the proposed dual-band slot antenna operating at 2.45 GHz WLAN band and 3.40-5.35 GHz band is fabricated on an FR4 substrate with a dimension of 30 mm by 30 mm. Experiment results show that the antenna has a desired impedance characteristic with a frequency band of 2.38-2.51 GHz and 3.32-5.38 GHz for a voltage standing wave < 2, and measured gain is 1.7 dBi at 2.45 GHz, and it ranges 2.4-3.2 dBi in the second band.

Dual-band Open Loop Antenna using Strip-conductor for the RFID and Wireless LAN Application (RFID 및 무선 LAN용 이중대역 도체스트립 개방루프 안테나)

  • Lim, Jung-Hyun;Kang, Bong-Soo;Kim, Heung-Soo;Jwa, Jeong-Woo;Yang, Doo-Yeong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.3 s.357
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    • pp.98-104
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    • 2007
  • In this paper, the dual-band open loop antenna using a strip conductor for the RFID reader and Wireless LAN Application, which has a resonant frequency at 910MHz and 2.45 GHz, is proposed. Input impedance of antenna is matched with the feed line of 50 ohm by varying the length and width of sip conductor making up the antenna. The gain and directivity of antenna is enhanced as tuning the length of strip, and as also grooving the teeth shapes on the strip conductor. The size of fabricated antenna is $75mm\times100mm$. The return loss and the gain of fabricated antenna are -11.92 dB, 3.02 dBi at 910 MHz and -21.31 dB, 4.08 dBi at 2.45 GHz, respectively.

LPG/LTR Method for Output-Delayed System (출력 시가 지연 시스템의 LQG/LTR 방법)

  • 이상정;홍석민
    • The Transactions of the Korean Institute of Electrical Engineers
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    • v.43 no.5
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    • pp.827-837
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    • 1994
  • This paper presents robustness propertis of the Kalman Fiter and the associated LQG/LTR method for linear time-invariant output-delayed systems. It is shown that, even for minimum phase plants, the LQG/LTR method can not recover the target loop transfer function. Instead, an upper bound on the recovery error is obtained using an upper bound of the solution of the Kalman filter Riccati equations. Finally, some dual properties between output-delayed systems and input-delayed systems are exploited.

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Laser Doppler Vibrometer with Self Vibration Compensation (자체 진동 보상기능을 가진 레이저 도플러 진동측정계에 관한 연구)

  • Lee, Young-Jin;Kim, Ho-Seong
    • Proceedings of the KIEE Conference
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    • 2001.11a
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    • pp.53-55
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    • 2001
  • A dual probe laser Doppler vibrometer (LDV) that has one laser source and provides two independent object beams has been developed for the first time. An electronic circuit that converts light signal to electronic signal has been also developed using phase locked loop(PLL). It was found that this types of dual probe LDV can be used in differential mode and self-vibration compensation mode.

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A New Phase Shift PWM Parallel-input/series-output Modularized Dual Converter (새로운 위상전이 병렬입력/직렬출력 모듈화를 적용한 듀얼 컨버터)

  • 노정욱
    • Proceedings of the KIPE Conference
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    • 2000.07a
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    • pp.270-273
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    • 2000
  • A new phase shift PWM parallel-input/series-output modularized dual converter is proposed in this paper. This converter is operated with a fixed duty ratio and its output voltage is regulated by phase shift between each module. Since the operating duty ratio of each module is fixed it is sufficient to implement a simple open loop drive circuitry for each module and the cost of total system can be much reduced. The operation of the converter is analyzed in this paper and verified by computer simulation.

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Laser Doppler Vibrometer with self vibration compensation (자체 진동 보상기능을 가진 레이저 도플러 진동측정계에 관한 연구)

  • Lee, Young-Jin;Kim, Ho-Seong
    • Proceedings of the KIEE Conference
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    • 2001.07c
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    • pp.1838-1840
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    • 2001
  • A dual probe laser Doppler vibrometer (LDV) that has one laser source and provides two independent object beams has been developed for the first time. An electronic circuit that converts light signal to electronic signal has been also developed using digital phase locked loop(DPLL). It was found that this types of dual probe LDV can be used in differential mode and self-vibration compensation mode.

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Design of a Triple-Mode Bandpass Filter Using a Closed Loop Resonator

  • Myung, Jae-Yoon;Yun, Sang-Won
    • Journal of electromagnetic engineering and science
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    • v.17 no.2
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    • pp.86-90
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    • 2017
  • In this study, a novel third-order bandpass filter, which is based on a rectangular closed loop resonator, is presented. By adding a series resonator to the conventional loop resonator, the resonator's even resonant mode is split into two modes, while the odd resonant mode is not affected. Therefore, by varying the values of the series resonator elements, the resonant frequencies of two even modes can be determined independent of the odd-mode resonant frequency. In the proposed triple-mode filter design, instead of using a lumped series resonator, a T-shaped transmission line is coupled to the resonator via a small gap. To verify the design method, a filter is designed at 2.4 GHz with a bandwidth of 100 MHz. The improved performances of the proposed triple-mode filter are compared with those of the conventional dual mode filter.

A Study on Low Phase Noise Frequency Synthesizer Design with Compact Size for High Frequency Band (고주파용 소형 저 위상잡음 주파수 합성기 설계에 관한 연구)

  • Kim, Tae-Young
    • Journal of the Korea Institute of Military Science and Technology
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    • v.15 no.4
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    • pp.450-457
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    • 2012
  • In this paper, we designed low phase noise frequency synthesizer with compact size for High frequency band (Ku-band). The paper addresses merits and demerits of single loop and dual loop frequency synthesizer. The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed model in this paper more accurately predicts the low phase noise frequency synthesizer with compact size for high frequency band.

Design of Low Voltage 1.8V, Wide Range 50∼500MHz Delay Locked Loop for DDR SDRAM (DDR SDRAM을 위한 저전압 1.8V 광대역 50∼500MHz Delay Locked Loop의 설계)

  • Koo, In-Jae;Chung, Kang-Min
    • The KIPS Transactions:PartA
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    • v.10A no.3
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    • pp.247-254
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    • 2003
  • This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.