• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.60 no.2
• /
• pp.320-324
• /
• 2011

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked loops. A 2 GHz charge pump PLL (CPPLL) is used to justify the proposed calibration technique. The proposed digital calibration technique is implemented simply using a counter. The proposed calibration technique reduces the calibration time by up to a maximum of 50% compared other with techniques. Also by using a dual-mode CP, good current matching characteristics can be achieved to compensate $0.5{\mu}A$ current mismatch in CP. It was designed in a standard $0.13{\mu}m$ CMOS technology. The maximum calibration time is $33.6{\mu}s$ and the average power is 18.38mW with 1.5V power supply and effective area is $0.1804mm^2$.

• Proceedings of the KIEE Conference
• /
• summer
• /
• pp.1034-1036
• /
• 2004

The most basic form of a direct-drive linear motor is the voice coil motor(VCM). The voice coil motor employs a stationary permanent magnet field assembly in conjunction with a moving coil winding assembly to produce a force proportional to the current applied to the coil. Voice coil motor provide motion capable of extremely fine position sensitivity, limited only by the feedback sensor used to close the control loop. This paper presents dual-servo voice coil motor for improvement of driving range and position resolution. The voice coil motor is a cylindrical shape to improve reliability of a nanoindenter.

• 한국정보통신설비학회:학술대회논문집
• /
• 2008.08a
• /
• pp.131-136
• /
• 2008

System을 통해 출력되는 신호를 측정할 때 정확한 측정을 방해하는 요소로 잡음이 있다. 이런 신호 측정의 방해 요소인 잡음을 제거 하는 방법 중의 하나로 Lock-in Amp(LIA)가 사용되고 있다. 본 논문에서는 잡음 신호의 제거를 위해 사용 하는 LIA를 제작 하고 특성을 파악 하였으며 RF통신을 이용하여 무선 형태로 제작 하였다. 현재 상용화된 LIA는 프로브를 통한 유선으로 측정신호의 입력을 받게 되지만 본 논문에서 제작된 LIA는 무선신호 형태로 입력 하게 된다. RF통신의 케리어 주파수는 447.9[MHz]로 Digital GMSK 변복조방식을 이용하였다. LIA의 제작은 Dual Phase Sensitive Detecter을 사용하였으며, 주요 구성 요소인 Phase Locked Loop, Phase Shifter, Phase Sensitive Detector, Low Pass Filter등의 구조와 특성을 조사하였다.

• Proceedings of the KIPE Conference
• /
• 2014.07a
• /
• pp.136-137
• /
• 2014

본 논문에서는 계통 전압이 불평형 및 왜곡되었을 경우에 정확한 위상각을 검출 할 수 있는 DSOGI-QSG(dual second order generalized integrator quadrature signal generation)를 이용한 PLL (phase locked loop) 방법을 제안한다. 제안된 PLL 방법은 기존의 DSOGI-PLL 방법과 비교하기 위해, 전압에 불평형 및 왜곡 사고 발생 시 동기각을 검출하는 시뮬레이션을 하였고, 이를 통해 THD가 개선됨을 입증하였다.

• Journal of the Optical Society of Korea
• /
• v.4 no.1
• /
• pp.14-18
• /
• 2000

We have investigated gain flattening of EDFA systems with or without a gain equalizer for WDM long-haul transmission using a re-circulating EDFA loop. Without a gain equalizer, gain variation as small as 2.9 dB was achieved over the 10-nm band of a 100 cascaded EDFA system by the inversion principle. With a gain equalizer based on all-fiber acousto-optic tunable filters, two different config-urations of EDFAs were tested. For a single-stage EDFA scheme, the 21-nm band has shown 3.8 dB of gain variation at 17.4 ∼ 20.3 dB of OSNRs after the 100the stage of EDFAs. For a dual-stage EDFA scheme, a wider bandwidth of 34 nm has shown 3.6-dB variation after 40 cascaded EDFAs.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.9-16
• /
• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.12
• /
• pp.8306-8313
• /
• 2015

Open-type current sensors have been commonly used for DC motor controller, AC variable controller and Uninterruptible Power Supply. Recently they have begun to be used more widely, as the growth of renewable energy and smart-grid in power system. Considering most of the open-type current sensors are imported, developing the core technology needed to produce open-type current sensors is required. This paper describes the development and test results of open-type current sensors. Design of C type magnetic core, selection and test of a Hall sensor, design of current source circuit and signal conditioning circuit are described. 100A class DIP(Dual In-line Package) type and SMD(Surface Mount Devide) type open-type current sensors was made and tested. Test results show that the developed open-type current sensor satisfies the accuracy requirement of 2% and linearity requirement of 2% at 100 A of DC and AC current of 60Hz. Temperature compensation was carried out by using a temperature compensation circuit with NTC(Negative Temperature Coefficient) thermistor and the effect of the temperature compensation are described.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.21 no.5
• /
• pp.475-485
• /
• 2010

This paper proposes a novel concept for a microstrip resonator that can function as a filter and as an antenna at the same time. The proposed structure consists of an outer ring, an open loop-type inner ring, a circular patch, and three ports. The frequencies where the proposed structure works as a filter and as an antenna, respectively, are determined primarily by the radius of the inner ring and the circular patch. The measured results show that, when the microstrip resonator operates as a filtering device, this filter has about 15.1 % bandwidth at the center frequency of 0.63 GHz and a minimum insertion loss of 1.5 dB within passband. There are three transmission zeros at 0.52 GHz, 1.14 GHz, and 2.22 GHz. In the upper stopband, cross coupling - taking place at the stub of the outer ring - and the open loop-type inner ring produce one transmission zero each. The circular patch generates the dual-mode property of the filter and another transmission zero, whose location can be easily adjusted by altering the size of the circular patch. The proposed structure works as an antenna at 2.7 GHz, showing a gain of 3.8 dBi. Compared to a conventional patch antenna, the proposed structure has a similar antenna gain. At the resonant frequencies of the filter and the antenna, high isolation(less than -25 dB) between the filter port and the antenna port can be obtained.

• Journal of Power Electronics
• /
• v.11 no.4
• /
• pp.408-417
• /
• 2011

The plug-in hybrid electric vehicles (PHEVs) are specialized hybrid electric vehicles that have the potential to obtain enough energy for average daily commuting from batteries. The PHEV battery would be recharged from the power grid at home or at work and would thus allow for a reduction in the overall fuel consumption. This paper proposes an integrated power electronics interface for PHEVs, which consists of a novel Eight-Switch Inverter (ESI) and an interleaved DC/DC converter, in order to reduce the cost, the mass and the size of the power electronics unit (PEU) with high performance at any operating mode. In the proposed configuration, a novel Eight-Switch Inverter (ESI) is able to function as a bidirectional single-phase AC/DC battery charger/ vehicle to grid (V2G) and to transfer electrical energy between the DC-link (connected to the battery) and the electric traction system as DC/AC inverter. In addition, a bidirectional-interleaved DC/DC converter with dual-loop controller is proposed for interfacing the ESI to a low-voltage battery pack in order to minimize the ripple of the battery current and to improve the efficiency of the DC system with lower inductor size. To validate the performance of the proposed configuration, the indirect field-oriented control (IFOC) based on particle swarm optimization (PSO) is proposed to optimize the efficiency of the AC drive system in PHEVs. The maximum efficiency of the motor is obtained by the evaluation of optimal rotor flux at any operating point, where the PSO is applied to evaluate the optimal flux. Moreover, an improved AC/DC controller based Proportional-Resonant Control (PRC) is proposed in order to reduce the THD of the input current in charger/V2G modes. The proposed configuration is analyzed and its performance is validated using simulated results obtained in MATLAB/ SIMULINK. Furthermore, it is experimentally validated with results obtained from the prototypes that have been developed and built in the laboratory based on TMS320F2808 DSP.

• Transactions of the Korean Society of Automotive Engineers
• /
• v.21 no.6
• /
• pp.81-91
• /
• 2013

A novel design process of a parallel multi-flow type air-cooled condenser of a dual-loop waste heat recovery system with Rankine steam cycles for improving the fuel efficiency of gasoline automobiles has been investigated focusing on reduction of the pressure drop inside the micro-tubes. The low temperature condenser plays a role to dissipate heat from the system by condensing the low temperature loop working fluid sufficiently. However, the refrigerant has low evaporation temperature enough to recover the waste from engine coolant of about $100^{\circ}C$ but has small saturation enthalpy so that excessive mass flow rate of the LT working fluid, e.g., over 150 g/s, causes enormously large pressure drop of the working fluid to maintain the heat dissipation performance of more than 20 kW. This paper has dealt with the scheme to design the low temperature condenser that has reduced pressure drop while ensuring the required thermal performance. The number of pass, the arrangement of the tubes of each pass, and the positions of the inlet and outlet ports on the header are most critical parameters affecting the flow uniformity through all the tubes of the condenser. For the purpose of the performance predictions and the parametric study for the LT condenser, we have developed a 1-dimensional user-friendly performance prediction program that calculates feasibly the phase change of the working fluid in the tubes. An example is presented through the proposed design process and compared with an experiment.