• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.2
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• pp.150-157
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• 2021

Nowadays, a DC microgrid that can link various distributed power sources is gaining much attention. Accordingly, research on fault situations, such as line-to-line and line-to-ground faults of the DC microgrid, has been conducted to improve grid reliability. However, the blackout of an AC system and the oscillation of a DC bus voltage have not been reported or have not been sufficiently verified by previous research. In this study, a 20 kW DC microgrid testbed using a power HIL simulation technique is proposed. This testbed can simulate various fault conditions without any additional grid facilities and dangerous experiments. It includes the blackout of the DC microgrid caused by the AC utility grid's blackout, a drastic load increment, and the DC bus voltage oscillation caused by the LCL filter of the voltage source converter. The effectiveness of the proposed testbed is verified by using Opal-RT's OP5707 real-time simulator with a 3 kW prototype three-port dual-active-bridge converter.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.5
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• pp.515-525
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• 2014

In this paper, we present a design and implementation of a Voltage-tuned Planar Composite Resonator Oscillator(Vt-PCRO) with a low phase noise. The designed Vt-PCRO is composed of a resonator, two phase shifters, and an amplifier. The resonator is designed using a dual mode SIW(Substrate Integrated Waveguide) resonator and has a group delay of about 40 nsec. Of the two phase shifters (PS1 and PS2), PS1 with a phase shift of $360^{\circ}$ is used for the open loop gain to satisfy oscillation condition without regard to the electrical lengths of the employed microstrip lines in the loop. PS2 with a phase shift of about $70^{\circ}$ is used to tune oscillation frequency. The amplifier is constructed using two stages to compensate for the loss of the open loop. Through the measurement of the open loop gain, the tune voltage of the PS1 can be set to satisfy the oscillation condition and the loop is then closed to form the oscillator. The oscillator with a oscillation frequency of 5.345 GHz shows a phase noise of -130.5 dBc/Hz at 100 kHz frequency offset. The oscillation power and the electrical frequency tuning range is about 3.5 dBm and about 4.2 MHz for a tuning voltage of 0~10 V, respectively.

• Journal of Advanced Navigation Technology
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• v.16 no.4
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• pp.571-577
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• 2012

In this paper, we design a flight controller using a dynamic compensator for a small unmanned aerial vehicle. The proposed method ensures flight stability during altitude holding and waypoints passing by improving the transient response and steady state error. The control system consists of dual feedback loops with an inner loop and a outer loop. The inner loop has a PD controller to improves the transient response and the outer loop has a dynamic compensator to reduce overshoot in the transient response and improve the steady state error. The performance of the proposed method is evaluated by flight test on a small UAV.

• Journal of Power Electronics
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• v.15 no.6
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• pp.1456-1467
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• 2015

This paper presents a novel close-loop control scheme based on small signal modeling and weighted composite voltage feedback for a three-phase input and single-phase output Matrix Converter (3-1MC). A small non-polar capacitor is employed as the decoupling unit. The composite voltage weighted by the load voltage and the decoupling unit voltage is used as the feedback value for the voltage controller. Together with the current loop, the dual-loop control is implemented in the 3-1MC. In this paper, the weighted composite voltage expression is derived based on the sinusoidal pulse-width modulation (SPWM) strategy. The switch functions of the 3-1MC are deduced, and the average signal model and small signal model are built. Furthermore, the stability and dynamic performance of the 3-1MC are studied, and simulation and experiment studies are executed. The results show that the control method is effective and feasible. They also show that the design is reasonable and that the operating performance of the 3-1MC is good.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.2
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• pp.27-35
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• 2016

A Low jitter dual output frequency synthesizer for smart audio devices is described in this paper. It has been fabricated in a 1.8 V Dongbu $0.18-{\mu}m$ CMOS process. Output frequency is controlled by 3 rd order Sigma-Delta Modulation and digital divider. The frequency synthesizer has a size of $0.6mm^2$, frequency range of 0.6-200 MHz, loop bandwidth of 350 kHz, and rms jitter of 11.4 ps-21.6 ps.

• Molecules and Cells
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• v.26 no.2
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• pp.200-205
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• 2008

The mitogen-activated protein kinase (MAPK) signaling pathway is activated in response to extracellular stimuli and regulates various activities in eukaryotic cells. Following exposure to stimuli, MAPK is known to be activated via dual phosphorylation at a conserved TxY motif in the activation loop; both threonine and tyrosine residues are phosphorylated by an upstream kinase. However, the mechanism underlying dual phosphorylation is not clearly understood. In the budding yeast Saccharomyces cerevisiae, the Hog1 MAPK mediates the high-osmolarity glycerol (HOG) signaling pathway. Tandem mass spectrometry and phosphospecific immunoblotting were performed to quantitatively monitor the dynamic changes occurring in the phosphorylation status of the TxY motif of Hog1 on exposure to osmotic stress. The results of our study suggest that the tyrosine residue is preferentially and dynamically phosphorylated following stimulation, and this in turn leads to the dual phosphorylation. The tyrosine residue was hyperphosphorylated in the absence of a threonine residue; this result suggests that the threonine residue is critical for the control of signaling noise and adaptation to osmotic stress.

• Journal of the Korean Society of Manufacturing Technology Engineers
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• v.25 no.1
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• pp.75-82
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• 2016

In this study, a cross-damped low vibration controller was developed to reduce vibration in ultra-precision dual stage driven by master/slave principle. In master-slave structure, the master stage leads the driving motion and the slave stage follows it so as to maintain a constant gap between two stages. In this structure, a small perturbation of master stage makes big oscillations in slave servoing stage, so a low damped master stage composed of voice coil motor makes a long vibration in settling area after driving motion profile. In this research, an effective feedback damping algorithm for increase the damping characteristics of the dual stage was developed. The designed velocity damping algorithm improves the system stability and reduces the settling time of the whole system. Simulation and experimental results show that the developed algorithm reduces settling time and improves the regulating performance.

• Earthquakes and Structures
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• v.3 no.5
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• pp.749-766
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• 2012

Structural control through integration of passive damping devices within the building structure has been increasingly implemented internationally in the last years and has proven to be a most promising strategy for earthquake safety. In the present paper an alternative configuration of an innovative energy dissipation mechanism that consists of slender tension only bracing members with closed loop and a hysteretic damper is investigated in its dynamic behavior. The implementation of the adaptable dual control system, ADCS, in frame structures enables a dual function of the component members, leading to two practically uncoupled systems, i.e., the primary frame, responsible for the normal vertical and horizontal forces and the closed bracing-damper mechanism, for the earthquake forces and the necessary energy dissipation. Three representative international earthquake motions of differing frequency contents, duration and peak ground acceleration have been considered for the numerical verification of the effectiveness and properties of the SDOF systems with the proposed ADCS-configuration. The control mechanism may result in significant energy dissipation, when the geometrical and mechanical properties, i.e., stiffness and yield force of the integrated damper, are predefined. An optimum damper ratio, DR, defined as the ratio of the stiffness to the yield force of the hysteretic damper, is proposed to be used along with the stiffness factor of the damper's- to the primary frame's stiffness, in order for the control mechanism to achieve high energy dissipation and at the same time to prevent any increase of the system's maximum base shear and relative displacements. The results are summarized in a preliminary design methodology for ADCS.