• Korean Journal of Social Welfare Studies
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• no.37
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• pp.199-240
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• 2008

This study set out to investigate the adaptation process and experiential structure of those children who went through sexual abuse by looking into their inner worlds in order to understand what kind of meaning sexual abuse had on them. For that, the investigator conducted in-depth interviews with 13 children aged 8~16 who lived at the shelter after experiencing sexual abuse. The methodology of Grounded Theory by Strauss and Corbin(1990) was used to analyze raw data. The analysis results indicate that the core theme of the adaptation process among the children living at the shelter after sexually abused by kin and kith was "hoping to appear the same as others." According to the results, the core phenomenon was "blaming the victims." The causal conditions include "broken families," "antihuman sexual abuse," "making sexual abuse a public issue," and "the trap of the family." The contextual conditions include "the chain named family," "family as the last fortress" and "structural enforcement of silence." The intervening strategies was "dual emotions toward the shelter." The action/interaction strategies include "aftermath of violence" and "trying to escape." The consequences were "preparation for the future" and "uncertain future." The identified stages include the confusion, keeping the secret, leaking the secret to others, intervention by others, social support and challenge and adjustment stage. The three identified types were "withdrawal and avoidance," "settling down in reality" and "overcoming and challenging." Based on the analysis results, discussions were made about the social welfare plans and intervention strategies in the conclusion.

• The Journal of Korean Philosophical History
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• no.58
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• pp.245-278
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• 2018

The paper has focused on examining the sense of educational process in the light of Xugua zhuan[序卦傳], the Sequence of the Hexagrams as one among Ten Wings in I Ching, particularly on the 11 Iching-hexagrams from ch'ien[乾] to t'ai[泰]. The process involved in this part of the Book of Change can be recognized as both the micro and macro levels, which can eventually leads us to construct the circular system of thought[環相型]. This gives us a possibility to consider the values of education beyond the dualism such as intrinsic and extrinsic as well as traditional and progressive ones. Particularly some crucial defects from child-centered education have been critically examined so that the concept of education can be taken seriously in the light of the teacher-side. Thus this provides us a necessity to dub 'education' as '敎育', not as '兒育' in the Oriental context. As shown in the paper, the cosmic dual forces of I Ching also enables us to dissolve some conflicts arisen in the educational welfare system and situations, and then shows us why we should respect for the teachers' stances though we have to consider the interests of children to be educated. Thus we need to re-examine the content of the Book in the link with the Western systems of educational theory.

• Journal of the Korea Society of Computer and Information
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• v.25 no.9
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• pp.63-69
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• 2020

Image-image translation is a technology that creates a target image through input images, and has recently shown high performance in creating a more realistic image by utilizing GAN, which is a non-map learning structure. Therefore, there are various studies on image-to-image translation using GAN. At this point, most image-to-image translations basically target one attribute translation. But the data used and obtainable in real life consist of a variety of features that are hard to explain with one feature. Therefore, if you aim to change multiple attributes that can divide the image creation process by attributes to take advantage of the various attributes, you will be able to play a better role in image-to-image translation. In this paper, we propose Multi CycleGAN, a dual attribute transformation structure, by utilizing CycleGAN, which showed high performance among image-image translation structures using GAN. This structure implements a dual transformation structure in which three domains conduct two-way learning to learn about the two properties of an input domain. Experiments have shown that images through the new structure maintain the properties of the input area and show high performance with the target properties applied. Using this structure, it is possible to create more diverse images in the future, so we can expect to utilize image generation in more diverse areas.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• Journal of Korean Society of Environmental Engineers
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• v.28 no.2
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• pp.207-215
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• 2006

This study evaluated the effect of ultrasonic irradiation on reducing membrane fouling for the treatment of chemically treated leachate and biologically treated leachate. The experiments on improvement of membrane flux according to the membrane types(MF and UF) and membrane materials were performed with changing frequency(40 kHz and 120 kHz) and intensity(200 W and 400 W) of ultrasound in ultrasonic membrane separation apparatus which ultrasound can be periodically irradiated. Additionally, the effect of dual frequency ultrasound which 40 kHz md 120 kHz are irradiated simultaneously was evaluated. The improvement of membrane flux by periodical ultrasound irradiation was higher in microfiltration(MF) membrane than in ultrafiltration(UF) membrane. It was sustained more in the MF membrane of polyvinylidene fluoride(PVDF) than in that of polysulfon(PS). Ultrasonic improvement of membrane flux was different depending on the characteristics of target wastewater. It was sustainably maintained without reclogging using dual frequency ultrasound although the improvement of membrane flux was lower.

• Journal of Advanced Navigation Technology
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• v.22 no.1
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• pp.31-36
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• 2018

In this paper, we designed and implemented an ultra wideband(UWB) antenna with band rejection characteristics. The proposed antenna consists of a planar radiation patch with slots and ground planes on both sides. Due to the slots in the radiation patch, the antenna shows band rejection characteristics. U-type slot contributes for wireless local area network(WLAN, 5.15~5.825 GHz) band rejection and n-type slot contributes for X-Band(7.25~8.395 GHz) band rejection. To make voltage standing wave ratio(VSWR) less than 2.0 for UWB frequency band except rejection bands, the shapes of planar radiation patch and ground plane was modified. The Ansoft 's high frequency structure simulator(HFSS) was used for the design process and simulations of the proposed antenna. The simulated antenna showed VSWR less than 2.0 for all UWB band excepts for dual rejection bands of 5.15 ~ 5.94 GHz and 7.02 ~ 8.45 GHz. And measured VSWR for the implemented antenna is less than 2.0 for all UWB band of 3.10~10.60 GHz excluding dual rejection bands of 5.12~5.95 GHz and 7.20~8.58 GHz.

• Journal of the Korea Society of Computer and Information
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• v.17 no.1
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• pp.31-40
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• 2012

u-GIS DSMSs have been researched to deal with various sensor data from GeoSensors in ubiquitous environment. Also, they has been more important for high availability. The data from GeoSensors have some characteristics that increase explosively. This characteristic could lead memory overflow and data loss. To solve the problem, various load shedding methods have been researched. Traditional methods drop the overloaded tuples according to a particular criteria in a single server. Tuple deletion sensitive queries such as aggregation is hard to satisfy accuracy. In this paper a dual processing load shedding method is suggested to improve the accuracy of aggregation in clustering environment. In this method two nodes use replicated stream data for high availability. They process a stream in two nodes by using a characteristic they share stream data. Stream data are synchronized between them with a window as a unit. Then, processed results are merged. We gain improved query accuracy without data loss.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.1
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• pp.75-82
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• 2000

In this paper, a new low power 16-bit ALU has been designed, fabricated and tested at the transistor level. The designed ALU performs 16 instructions and has a two-stage pipelined architecture. For the reduction of switched capacitance, the ELM adder of the proposed ALU is inactive while the logical operation is performed and P(propagation) block has a dual bus architecture. A new efficient P and G(generation) blocks are also proposed for the above ALU architecture. ELM adder, double-edge triggered register and the combination of logic style are used for low power consumption as well. As a result of simulations, the proposed architecture shows better power efficient than conventional architecture$^{[1,2]}$ as the number of logic operation to be performed is increased over that of arithmetic to logic operation to be performed is 7 to 3, compared to conventional architecture. The proposed ALU was fabricated with 0.6${\mu}m$ single-poly triple-metal CMOS process. As a result of chip test, the maximum operating frequency is 53MHz and power consumption is 33mW at 50MHz, 3.3V.