• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.4
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• pp.407-411
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• 1998

Traditional carrier-based PWM method cannot produce maximum output voltage due to dead-time compensation, w which results in degradation of voltage utilization factor compared with ideal PWM inverters, Dual-carrier PWM has b been proposed as an alternative method to solve this problem. But this method requires paying attentition to changing r reference voltage in the vicinity of maximum voltage to ensure enough dead-time. Novel dual-carrier PWM method and i it's practical implementation is proposed in this paper. The reference voltage can be changed without any restriction in t this method.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.421-422
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• 2015

Nowadays, bidirectional DC-DC converters are becoming more into picture for different applications especially electric vehicles. There are many bidirectional DC-DC converters topologies; however, voltage-fed Dual Half-Bridge (DHB) topology has less number of switches as compared to other isolated bidirectional DC-DC converters. Furthermore, voltage fed DHB has galvanic isolation, high power density, reduced size, high efficiency and hence cost effective. Electrolytic capacitors always have problem regarding size and reliability in DC-AC single phase inverters. Therefore, voltage-fed DHB converter is proposed for the purpose of power decoupling to replace electrolytic capacitor by film capacitors. A new control strategy has been developed for 120Hz ripple rejection, and it was verified by simulation.

• Journal of Power Electronics
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• v.19 no.6
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• pp.1403-1412
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• 2019

A coupled inductor-dual boost-inverter (CIDBI) with a differential structure has been presented for application to a micro-inverter photovoltaic module system due to its turn ratio of a high-voltage level. However, it is difficult to design a CIDBI converter with a conventional PI regulator to be stable and achieve good dynamic performance, given the fact that it is a high order system. In view of this situation, a sliding mode control (SMC) strategy is introduced in this paper, and two different sliding mode controllers (SMCs) are proposed and adopted in the left and right side of two Boost sub-circuits to implement the corresponding regulation of the voltage and current. The schemes of the SMCs have been elaborated in this paper including the establishment of a system variable structure model, selection of the sliding surface, determination of the control law, and presentation of the reaching conditions and sliding domain. Finally, the mathematic analysis and the proposed SMC are verified by experimental results.

• Journal of Electrical Engineering and Technology
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• v.11 no.1
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• pp.143-149
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• 2016

The two-stage converter is widely used in traditional DC/AC inverter. It has several disadvantages such as complex topology, large volume and high loss. In order to overcome these shortcomings, a novel half load-cycle worked dual SEPIC single-stage inverter, which is based on the analysis of the relationship between input and output voltages of SEPIC converters operating in the discontinuous conduction mode (DCM), is presented in this paper. The traditional single-stage inverter has remarkable advantages in small and medium power applications, but it can’t realize boost DC/AC output directly. Besides one pre-boost DC/DC converter is needed between the DC source and the traditional single-stage inverter. A novel DC/AC inverter without pre-boost DC/DC converter, which is comprised of two SEPIC converters, is studied. The output of dual SEPIC converters is connected with anti-parallel and half load-cycle control is used to realize boost and buck DC/AC output directly and work properly, whatever the DC input voltage is higher or lower than the AC output voltage. The working principle, parameter selection and the control strategy of the inverters are analyzed in this paper. Simulation and experiment results verify the feasibility of the new inverter.

• Journal of Power Electronics
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• v.17 no.1
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• pp.67-75
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• 2017

Due to the excessive zero-sequence voltage in dual three-level inverter fed open-end winding induction motor systems, zero-sequence circumfluence which is harmful to switching devices and insulation is then formed when operating in a single DC voltage source supplying mode. Traditionally, it is the mean value instead of instantaneous value of the zero-sequence voltage that is eliminated, through adjusting the durations of the operating vectors. A new strategy is proposed for zero-sequence voltage elimination, which utilizes unified voltage modulation and a decoupled SVPWM strategy to achieve two same-sized equivalent vectors for an angle of $120^{\circ}$, generated by two inverters independently. Both simulation and experimental results have verified its efficiency in the instantaneous value elimination of zero-sequence voltage.

• Journal of Power Electronics
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• v.15 no.4
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• pp.910-919
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• 2015

The use of a PV grid-connected inverter with non-isolated topology and without a transformer is good for improving conversion efficiency; however, this inverter has become increasingly complicated for eliminating leakage current. To simplify the complicated architecture of traditional three-level dual buck inverters, a new dual Buck three-level PV grid-connected inverter topology is proposed. In the proposed topology, the voltage on the grounding stray capacitor is clamped by large input capacitors and is equal to half of the bus voltage; thus, leakage current can be eliminated. Unlike in the traditional topology, the current in the proposed topology passes through few elements and does not flow through the body diodes of MOSFET switches, resulting in increased efficiency. Additionally, a multi-loop control method that includes voltage-balancing control is proposed and analyzed. Both simulation and experimental results are demonstrated to verify the proposed structure and control method.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of Power Electronics
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• v.14 no.2
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• pp.315-323
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• 2014

An optimized space vector pulse width modulation (SVPWM) method with common mode voltage elimination and neutral point potential balancing is proposed for an open-end winding induction motor. The motor is fed from both of the ends with two neutral point clamped (NPC) three-level inverters. In order to eliminate the common mode voltage of the motor ends and balance the neutral point potential of the DC link, only zero common mode voltage vectors are used and a balancing control factor is gained from calculation in the strategy. In order to improve the harmonic characteristics of the output voltages and currents, the balancing control factor is regulated properly and the theoretical analysis is provided. Simulation and experimental results show that by adopting the proposed method, the common mode voltage can be completely eliminated, the neutral point potential can be accurately balanced and the harmonic performance for the output voltages and currents can be effectively improved.

• Journal of Power Electronics
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• v.13 no.5
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• pp.806-813
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• 2013

This paper aims to compare the performance of three phase induction motor drives using Five Leg Inverter (FLI) and Three Leg Inverter (TLI) configurations. An Indirect Field Oriented Control (IFOC) method using a TLI is well established and incorporated for high performance speed drives in various industries. The FLI dual motor drive system on the other hand shows good workability in the independent control of two induction motor drives simultaneously. In this experiment, the IFOC method is utilized for both drive systems, and Space Vector Pulse Width Modulation (SVPWM) is used to generate pulses for both inverters. For the FLI, the Double Zero Sequence (DZS) Injection technique is used to generate the modulation signal. The complete experiment setup is done by using a DSpace 1103 controller board. The individual motor performances are analyzed using similar schemes, equipment setups and controller parameter values. The results show similar speed performance response capability between the single motor operation using a TLI system and the two motor operation using a FLI system based on the variable speed range either in forward or reverse operation. They also show similar load rejection abilities. However, the single motor with a TLI has a better power quality aspect such as ripple current and total harmonics distortion (THD).

• Journal of Power Electronics
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• v.10 no.2
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.