• Journal of Navigation and Port Research
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• v.27 no.5
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• pp.505-511
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• 2003

In this paper, a driving amplifier stage with 1 Watt output has been designed and fabricated, which is operating at UHF band( 470 ∼ 806 MHz) for digital TV repeater. In the driving amplifier stage, preamplifier and 1 Watt unit amplifier are integrated by one electric substrate which is 2.53 in dielectric constant and 0.8 mm thickness. When the driving amplifier stage is flown by bias voltage of 28 V DC and current of 900 mA. it has the gain of more than 53.5 dB. the gain flatness of $\pm$0.5 dB and return loss of less than -15 dB in 470 ∼ 806 MHz. Also, when two signals at 2 MHz frequency interval are input port into the driving amplifier stage with 1 Watt output, it resulted in excellent characteristics to designed specification with showing intermodulation distortion characteristics of more than 48 dBc.

• ETRI Journal
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• v.35 no.2
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• pp.226-233
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• 2013

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only $0.4{\mu}W$ from a supply voltage of ${\pm}0.6V$ and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using $0.18-{\mu}m$ CMOS technology.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.113-117
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• 2003

This paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard $0.25{\mu}m$ CMOS technology and is shown to deliver 100mW output power to load with 41% power added efficiency(PAE) from a 2.5V supply.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.335-339
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• 2003

This Paper describes the design and the simulation results of the RF CMOS Class-E Power Amplifier for a 2.4GHz ISM band. This circuit is composed two connected amplifiers. where Class F amplifier drives Class E amplifier. The proposed circuit can reduce the total power dissipation of the driving stage and can work with higher efficiency. The power amplifier has been implemented in a standard 0.25$\mu\textrm{m}$ CMOS technology and is shown to deliver 100mW output Power to load with 41％ power added efficiency(PAE) from a 2.5V supply.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.5
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• pp.2241-2248
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• 2011

This paper describes the design of a palette-type 60watt high power amplifier module using gallium nitride(GaN) devices with high power and efficiency performances for WiMAX and LTE systems. The line-up for the high gain amplifier module consists of the pre-amplifier stage with low power and high gain, 8watt GaN driving amplifier stage, and 60watt GaN high power amplifier stage of Doherty structure with two 30watt GaN devices. The obtained gain is 61.4dB with an excellent gain flatness of ${\pm}$0.075dB over 2.5~2.68GHz. GaN devices and the Doherty structure are adopted for the improvement of high efficiency and output power. The measurement for the fabricated high power amplifier module of palette type is performed using the widely known WiMAX signal all over the world. In the example of RRH(remote radio head) application of the fabricated amplifier module, the measured efficiency is 37~38% with the 10watts of modulated output power. It is shown that when the fabricated amplifier module is activated with a digital predistorter(DPD), the measured ACLR is better than 46dBc under the 10watts of modulated output power.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.3
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• pp.56-61
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• 1996

In this paper, new buck converter of a TV power system is presented. First, we devised a revised driving circuit for an emitter-coupled type buck converter, by which it is possible to reduce the material cost of transformers and voltage stress of power device. Secondly, we adopted a hybrid oscillation technique. When TV system is in off-stage, initial standby power which is necessary for remote controllable TV system is supplied by self-oscillating mode. Main power which is necessry in TV system bing on state is provided by an externally triggered oscillating mode. The switching frequency is synchronized to the oscillating frequency of horizontal deflection in TV, by which we can reduce picture noises and the size of power transformer. Thirdly, a simple error amplifier is inserted to the feed-back loop to keep the output voltage constant which means pulse width modulatio mode is added in driving part of power device. Finally, we showed by experiments that our proposed converter performs well enough to be close to the theoretically predicted values.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.629-631
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• 2004

The proposed output buffer is presented for driving large-size LCD panels. This output buffer is designed by adding some simple circuitry to the conventional two-stage operational amplifier. The proposed circuit is simulated in a high-voltage 0.35um CMOS process with HSPICE. The simulated result is more improved settling time than that of conventional one.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.791-794
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• 2003

The increasing computational capability of processors is driving the need for high bandwidth links to communicate and store the information that is processed. Such links are often an important part of multi processor interconnection, processor-to-memory interfaces and Serial-network interfaces. This paper describes a 0.11-${\mu}{\textrm}{m}$ CMOS 4 Gbp s/pin 3-Level transceiver using RSL/(Rambus Signaling Logic) for high bandwidth. This system which uses a high-gain windowed integrating receiver with wide common-mode range which was designed in order to improve SNR when operating with the smaller input overdrive of 3-Level. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by low pass effects of channel, process-limited on-chip clock frequency, and serial link distance. In order to detect the transmited 4Gbps/pin with 3-Level data sucessfully ,the receiver is designed using 3-stage sense amplifier. The proposed transceiver employes multi-level signaling (3-Level Pulse Amplitude Modulation) using clock multi phase, double data rate and Prbs patten generator. The transceiver shows data rate of 3.2 ~ 4.0 Gbps/pin with a 1GHz internal clock.

• Journal of IKEEE
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• v.22 no.2
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• pp.408-412
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• 2018

In this paper, a 26GHz variable gain amplifier fabricated using a 40nm CMOS process is studied. In the case of an automobile radar using 79 GHz, it is advantageous in designing and driving to drive down to a low frequency band or to use a low frequency band before up conversion rather than designing and matching the entire circuit to 79 GHz in terms of frequency characteristics. In the case of a Phased Array System that uses time delay through TTD (True Time Delay) in practice, down conversion to a lower frequency is advantageous in realizing a real time delay and reducing errors. For a VGA (Variable Gain Amplifier) operating in the 26GHz frequency band that is 1/3 of the frequency of 79GHz, VDD : 1V, Bias 0.95V, S11 is designed to be <-9.8dB (Mea. High gain mode) and S22 < (Mea. high gain mode), Gain: 2.69dB (Mea. high gain mode), and P1dB: -15 dBm (Mea. high gain mode). In low gain mode, S11 is <-3.3dB (Mea. Low gain mode), S22 <-8.6dB (Mea. low gain mode), Gain: 0dB (Mea. low gain mode), P1dB: -21dBm (Mea. Low gain mode).