• Journal of Information Display
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• v.7 no.3
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• pp.5-8
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• 2006

A novel a-Si TFT integrated gate driver circuit using multi-thread driving has been developed. The circuit consists of two independent shift registers alternating between the two modes, "wake" and "sleep". The degradation of the circuit is retarded because the bias stress is removed during the sleep mode. It has been successfully integrated in 14.1-in. XGA LCD Panel, showing enhanced stability.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.4
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• pp.388-396
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• 2005

SRM has not been put into practical applications widely because of its large torque ripple, acoustic noise and low power factor. In addition, a traditional position sensor is needed for the drive control. So we propose an improved sensorless drive method of Switched Reluctance Motors using impressed voltage pulses. Conventional impressed voltage pulse method has a problem of phase delay because of low-pass filter. So in this paper we propose an unproved sensorless driving method based on the impressed voltage pulse using new pulse-shift circuit technique that overcomes the phase delay and start-up problem. Proposed method is implemented in a simple analog circuit instead of using an expensive DSP.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.52-56
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• 2009

In this research, we have studied the development of dc-dc converter suitable for the driving of mobile instruments by using a dye-sensitized solar cell(DSC). We also have designed a interlocking circuit. The circuit makes power generation be saved in one battery and concurrently be discharged in the other battery. As this application, mobile devices such as MP3, cellular phone are operated by using power generator from DSC during the daytime and they can be operated by using the saving energy of the daytime during the night. Consequently, it has a simple and robust circuit configuration. Besides, we designed dc-dc converter circuit to drive low power instruments by using NMOS switch and PMOS rectifier. Operational modes are analysed, and then validity of the proposed interface circuit is verified through DCS.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.93-95
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• 2005

A new energy-recovery- sustain circuit suitable for a Plasma Display Panel(PDP) application is proposed. The proposed circuit features the low device voltage stresses, essential to design a power efficient and low cost PDP driver circuit. The proposed circuit is demonstrated experimentally for driving a 42 inches plasma display panel.

• Journal of Information Display
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• v.2 no.4
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• pp.63-67
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• 2001

The switching power loss due to the panel capacitance during sustain period in AC PDP driving system can be minimized by using the energy recovery circuits. We proposed a new energy recovery circuit, SER1 (Seoul national univ. Energy Recovery circuit 1st). The experimental results of its application to a 42-inch surface discharge type AC PDP showed superior performance of SER1 in energy recovery efficiency and low distortion voltage waveform. Energy recovery efficiency of SER1 was measured up to 92.3 %, and the power dissipation during the sustain period was reduced by 15.2 W in 2000 pulse/frame compared with serial LC resonance energy recovery circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.2
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• pp.465-470
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• 1999

This paper presents a design method of driving system for EV(Electric Vehicle). EV driving system consist of batteries, battery interface system and inverter. The power control circuit of the driving system is simple, since only one PWM(Pulse Width Modulation) inverter is used. These test spectrums and waveforms can be used to determine the filter component ratings as well as to compute the harmonics injected into the source. The hybrid control strategy which can reduced harmonic components. The analysis results indicate that the required capacity of the condenser can be reduced with LC filter. In this paper, the design and implementation of the proposed systems are described and some experimental results are given to show the performance of this driving system. The control strategy of the system to available inverter's power and motor's power and torque is discussed.

• Journal of Power Electronics
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• v.14 no.2
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• pp.217-225
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• 2014

This paper deals with the optimization of the driving techniques for the ZVT synchronous buck converter proposed in [1]. Two new gate drive circuits are proposed to allow this converter to operate by only one control signal as a 12V voltage regulator module (VRM). Voltage-driven method is applied for the synchronous rectifier. In addition, the control signal drives the main and auxiliary switches by one driving circuit. Both of the circuits are supplied by the input voltage. As a result, no supply voltage is required. This approach decreases both the complexity and cost in converter hardware implementation and is suitable for practical applications. In addition, the proposed SR driving scheme can also be used for many high frequency resonant converters and some high frequency discontinuous current mode PWM circuits. The ZVT synchronous buck converter with new gate drive circuits is analyzed and the presented experimental results confirm the theoretical analysis.

• Journal of the Korean Society of Industry Convergence
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• v.10 no.4
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• pp.227-233
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• 2007

In case of design of a rectifier to supply high current, To select switching frequency of semiconductor switches affect absolutely the design of the LC filter value in an power conversion circuit. The conventional rectifier by using MOSFET is no use in high current equipments because of small drain-source current. To solve this problem, this paper proposes to design of high capacity rectifier by parallel driving of MOSFET in the single half bridge DC-DC converter. This method can be able to develop high current rectifier by distributed drain-source current. The proposed scheme is able to expect a decrease in size, weight and cost of production by decreasing the LC filter value and increasing maximumly the switching frequency. The validity of the proposed parallel driving strategy is verified through computer-aided simulations and experimental results.

• Journal of Korean Vacuum Science & Technology
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• v.3 no.1
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• pp.66-73
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• 1999

In this paper, the design of one-chip FED system integrated with driving circuits in reported on the basis of MOSFET controlled FEA (MCFEA). To integrate a MOSFET with a FEA efficiently, a new fabrication process is proposed. It is confirmed that the MOSFET with threshold voltage of about 2volts controls the FEA emission current up to 20 ${\mu}$A by applying driving voltage of 15 volts, which is enough current level to utilize the MCFEA as a pixel for FED. The drain breakdown voltage of the MOSFET is measured to be 70 volts, which is also high enough for 60 volt operation of FED. The circuits for row and column driver are designed stressing on saving area, reducing malfunction probability and consuming low power to maximize the merit of on-chip driving circuits. Dynamic logic concept and bootstrap capacitors are used to meet these requirements. By integrating the driving circuit with FEA, the number of external I/O lines can be less than 20, irrespectively of the number of pixels.