• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.6
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• pp.467-478
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• 2019

This paper describes the development and measurement results of a wide-band planar active phase array antenna system for an electronic warfare jamming transmitter. The system is designed as an $8{\times}8$ triangular lattice array using a $45^{\circ}$ slant wide-band antenna. The 64-element transmission channel is composed of a wide-band gallium nitride(GaN) solid state power amplifier and a gallium arsenide(GaAs) multi-function core chip(MFC). Each GaAs MFC includes a true-time delay circuit to avoid a wide-band beam squint, a digital attenuator, and a GaAs drive amplifier to electronically steer the transmitted beam over a ${\pm}45^{\circ}$ azimuth angle and ${\pm}25^{\circ}$ elevation angle scan. Measurement of the transmitted beam pattern is conducted using a near-field measurement facility. The EIRP of the designed system, which is 9.8 dB more than the target EIRP performance(P), and the ${\pm}45^{\circ}$ azimuth and ${\pm}25^{\circ}$ elevation beam steering fulfill the desired specifications.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.339-342
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• 2004

본 논문은 밀리미터파 대역 무선통신 시스템 송신부의 응용을 위해 CPW 구조를 이용하여 V-band용 상향 주파수 혼합기와 2단 구동증폭기를 설계$\cdot$제작하였다. 능동소자는 본 연구실에서 제작한 $0.1{\mu}m$ 게이트 GaAs Pseudomorphic HEMTs(PHEMTs)를 사용하였으며 입$\cdot$출력단은 CPW를 사용해 정합 회로를 설계하였다. 제작된 상향 주파수 혼합기는 LO power 5.4 dBm, 2.4 GHz IF 신호를 -10.25 dBm으로 입력하였을 때 Conversion Loss 1.25 dB, LO-to-RF Isolation은 58 GHz에서 13.2 dB의 특성을 나타내었다 2단 구동 증폭기는 측정결과 60 GHz에서 S21 이득 13 dB, $58\;GHz\;\~\;64\;GHz$ 대역에서 S21 이득 12 dB 이상을 유지하는 광대역 특성을 얻었고 증폭기의 Pl dB는 3.8 dBm, 최대 출력전력은 6.5 dBm의 특성을 얻었다.

• The Journal of the Acoustical Society of Korea
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• v.32 no.4
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• pp.287-293
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• 2013

We present a parametric array signal generating system using $3{\times}16$ transducer array which is composed of multi-resonant frequency transducers of 20kHz and 32.5kHz. To drive transducer array, sixteen channel amplifier using LM1875 chips is designed and implemented, and the PXI system based on the LabView 8.6 for arbitrary signal generation and analysis is used. Using the proposed system, we measure sound pressure level and beam pattern of difference frequency and verify the nonlinear effect of difference frequency. The theoretical absorption range and the Rayleigh distance are 15.51m and 1.933m, respectively and we verify that sound pressure of difference frequency is accumulated and increased at the near-field shorter than the Rayleigh distance. We verify that the beam pattern of the measured difference frequency and the beam pattern obtained by the superposition of two primary frequencies are similar, and high directional parametric signal was generated.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.9
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• pp.825-833
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• 2016

This paper introduces a direct-conversion CMOS RF transmitter for the IEEE 802.15.4 standard with a low-power high-gain up-conversion mixer designed in $0.18{\mu}m$ process. The designed RF DCT(Direct Conversion Transmitter) is composed of differential DAC(Digital to Analog Converter), passive low-pass filter, quadrature active mixer and drive amplifier. The most important characteristic in designing RF DCT is to satisfy the 2.4 GHz Zigbee standard in low power. The quadrature active mixer inside the proposed RF DCT provides enough high gain as well as sufficient linearity using a gain boosting technique. The measurement results for the proposed transmitter show very low power consumption of 7.8 mA, output power more than 0 dBm and ACPR (Adjacent Channel Power Ratio) of -30 dBc.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.726-729
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• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.14 no.4
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• pp.268-275
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• 2014

In future, hospitals are expected to automatically issue remote transcriptions. Many general hospitals are planning to encrypt their medical database to secure personal information as mandated by law. The electronic medical record system, picture archiving communication system, and the clinical data warehouse, amongst others, are the preferred targets for which stronger security is planned. In the near future, medical systems can be assumed to be automated and connected to remote locations, such as rural areas, and islands. Connecting patients who are in remote locations to medical complexes that are usually based in larger cities requires not only automatic processing, but also a certain amount of security in terms of medical data that is of a sensitive and critical nature. Unauthorized access to patients' transcription data could result in the data being modified, with possible lethal results. Hence, personal and sensitive data on telemedicine and medical information systems should be encrypted to protect patients from these risks. Login passwords, personal identification information, and biological information should similarly be protected in a systematic way. This paper proposes the use of electronic acupuncture with a built-in multi-pad, which has the advantage of being able to establish a patient's physical condition, while simultaneously treating the patient with acupuncture. This system implements a sensing pad, amplifier, a small signal drive circuit, and a digital signal processing system, while the use of a built-in fuzzy technique and a control algorithm have been proposed for performing analyses.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1297-1306
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• 2012

This work presents a 77 GHz radar transmitter for the automotive radar system. An integrated 13 GHz frequency synthesizer fabricated using 130 nm RF CMOS process drives a commercial W-band compound semiconductor monolithic multifunction amplifier(MPA), which includes a frequency multiplier by six to generate 77 GHz transmitting signal. The 13 GHz frequency synthesizer includes a high efficiency injection buffer of 4 dBm output power to drive the MPA. The output power of 77 GHz radar transmitter is higher than 13.99 dBm and the magnitude of the reference spur relative to the carrier is -36.45 dBc. The phase noise is -81 dBc/Hz at 1 MHz offset frequency from the carrier.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.6
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• pp.670-680
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• 2010

A low power single-chip CMOS receiver for 60 GHz mobile application are proposed in this paper. The single-chip receiver consists of a 4-stage current re-use LNA with under 4 dB NF, Cgs compensating resistive mixer with -9.4 dB conversion gain, Ka-band low phase noise VCO with -113 dBc/Hz phase noise at 1 MHz offset from 26.89 GHz, high-suppression frequency doubler with -0.45 dB conversion gain, and 2-stage current re-use drive amplifier. The size of the fabricated receiver using a standard 0.13 ${\mu}m$ CMOS technology is 2.67 mm$\times$0.75 mm including probing pads. An RF bandwidth is 6.2 GHz, from 55 to 61.2 GHz and an LO tuning range is 7.14 GHz, from 48.45 GHz to 55.59 GHz. The If bandwidth is 5.25 GHz(4.75~10 GHz) The conversion gain and input P1 dB are -9.5 dB and -12.5 dBm, respectively, at RF frequency of 59 GHz. The proposed single-chip receiver describes very good noise performances and linearity with very low DC power consumption of only 21.9 mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.11
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• pp.1566-1573
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• 2016

This paper presents a beam-forming receiver with polyphase In-phase/Quadrature-phase (I/Q) network for airborne communication. In beam-forming receiver, the insertion loss (IL) difference between input path increases the receiver noise figure (NF). The major element for generating IL difference is the impedance variation of phase shifter. In order to maintain a constant IL in every phase, this paper propose a lossless polyphase I/Q network based beam-forming receiver. The proposed lossless polyphase I/Q network has low Q-factor and high impedance for drive back-end VGA (Variable gain amplifier) block with low insertion loss. The 2-stage VGA controls in-phase and quadrature-phase amplitude level for vector summation. The proposed beam-forming receiver prototype is fabricated in TSMC $0.18{\mu}m$ CMOS process. The prototype cover the $360^{\circ}$ with $5.6^{\circ}$ LSB. The average RMS phase error and amplitude error is approximately $1.6^{\circ}$ and 0.3dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.