• 마이크로전자및패키징학회지
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• 제24권3호
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• pp.7-11
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• 2017

본 논문은 3차원 낸드 플래쉬 기억 소자에 적용을 위해 소노스(SONOS) 형태로 기억 저장 절연막을 채용하고 채널로 폴리실리콘을 사용한 박막형 트랜지스터에 대해 연구하였다. 셀의 source/drain에는 불순물을 주입 하지 않았고, 셀 양 끝단에는 선택 트랜지스터를 배치하였다. 셀의 채널과 선택 트랜지스터의 source/drain 불순물 농도 변화에 대한 평가를 진행하여 공정 최적화를 하였다. 선택 트랜지스터의 농도 증가 시 채널 전류의 상승 및 삭제특성이 개선됨을 확인 하였는데 이는 GIDL에 의한 홀 생성이 증가하였기 때문이다. 최적화된 공정 변수에 대해 삭제와 쓰기 후 문턱전압의 프로그램 윈도우는 대략 2.5V를 얻었다. 터널 산화막 공정 온도에 대한 평가 결과 온도 증가 시 swing 및 신뢰성 항목인 bake 결과가 개선됨을 확인하였다.

• 전자공학회논문지C
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• 제34C권8호
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• Journal of information and communication convergence engineering
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• 제5권1호
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• pp.45-49
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• 2007

The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

• 전자공학회논문지A
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• 제29A권2호
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• 전자공학회논문지A
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• 제33A권4호
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• pp.112-120
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• 1996

With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

• 한국전기전자재료학회논문지
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• 제33권4호
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• pp.281-285
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• 2020

Oxide semiconductor devices have become increasingly important because of their high mobility and good uniformity. The channel length of oxide semiconductor thin film transistors (TFTs) also shrinks as the display resolution increases. It is well known that reducing the channel length of a TFT is detrimental to the current saturation because of drain-induced barrier lowering, as well as the movement of the pinch-off point. In an organic light-emitting diode (OLED), the lack of current saturation in the driving TFT creates a major problem in the control of OLED current. To obtain improved current saturation in short channels, we fabricated indium gallium zinc oxide (IGZO) TFTs with single gate and double gate structures, and evaluated the electrical characteristics of both devices. For the double gate structure, we connected the bottom gate electrode to the source electrode, so that the electric potential of the bottom gate was fixed to that of the source. We denote the double gate structure with the bottom gate fixed at the source potential as the BGFP (bottom gate with fixed potential) structure. For the BGFP TFT, the current saturation, as determined by the output characteristics, is better than that of the conventional single gate TFT. This is because the change in the source side potential barrier by the drain field has been suppressed.

• Journal of information and communication convergence engineering
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• 제7권3호
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• pp.361-365
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• 2009

This paper has been presented the transport characteristics of FinFET using the analytical potential model based on the Poisson's equation in subthreshold and threshold region. The threshold voltage is the most important factor of device design since threshold voltage decides ON/OFF of transistor. We have investigated the variations of threshold voltage and drain induced barrier lowing according to the variation of geometry such as the length, width and thickness of channel. The analytical potential model derived from the three dimensional Poisson's equation has been used since the channel electrostatics under threshold and subthreshold region is governed by the Poisson's equation. The appropriate boundary conditions for source/drain and gates has been also used to solve analytically the three dimensional Poisson's equation. Since the model is validated by comparing with the three dimensional numerical simulation, the subthreshold current is derived from this potential model. The threshold voltage is obtained from calculating the front gate bias when the drain current is $10^{-6}A$.

• 한국광학회:학술대회논문집
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• 한국광학회 2000년도 하계학술발표회
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• pp.162-163
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• 2000

We have observed the short-channel effect, narrow-channel effect and small-geometry effect in terms of a variation of the threshold voltage. For a short-channel effect the threshold voltage was largely determined by the DIBL effect which stimulates more carrier injection in the channel by reducing the potential barrier between the source and channel. The effect becomes more significant for a shorter-channel device. However, the potential, field and current density distributions in the channel along the transverse direction showed a better uniformity for shorter-channel devices under the same voltage conditions. The uniformity of the current density distribution near the drain on the potential minimum point becomes worse with increasing the drain voltage due to the enhanced DIBL effect. This means that considerations for channel-width effect should be given due to the variation of the channel distributions for short-channel devices. For CCDs which are always operated at a pinch-off state the channel uniformity thus becomes significant since they often use a device structure with a channel length of > 4 ${\mu}{\textrm}{m}$ and a very high drain (or diffusion) voltage. (omitted)

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.918-921
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• 1999

The breakdown voltage in fully depleted SOI N-MOSFET’s have been studied over a wide range of film thicknesses, channel doping, and channel lengths. An asynmmetric Source/Drain SOI technology is proposed, which having the advantages of Normal LDD SOI(Silicon-On-Insulator) for breakdown voltage and gives a high drivability of LDD SOI without sacrificings hot carrier immunity The two-dimensional simulations have been used to investigate the breakdown behavior in these device. It is found that the breakdown voltage(BVds) is almost same with high current drivability as that in Normal LDD SOI device structure.