• E2M - 전기 전자와 첨단 소재
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• 제8권5호
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• pp.626-632
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• 1995

In this paper, The effect of the impedances in SNOSFET's memory devices has been developed. The effect of source and drain impedances measured by means of two bias resistances - field effect bias resistance by inner region, external bias resistance. The effect of the impedances by source and drain resistance shows the dependence of the function of voltages applied to the gate. It shows the differences of change in source drain voltage by means of low conductance state and high conductance state. It shows the delay of threshold voltages. The delay time of low conductance state and high conductance state by the impedances effect shows 3[.mu.sec] and 1[.mu.sec] respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권3호
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• pp.206-209
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• 2006

This paper presents an analytical noise model for the drain thermal noise, the induced gate noise, and their correlation coefficient in deep-submicron MOSFETs, which is valid in both linear region and saturation region. The impedance field method was used to calculate the external drain thermal noise current. The effect of channel length modulation was included in the analytical equation. The noise behavior of MOSFETs with decreasing channel length was successfully predicted from our model.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1995년도 춘계학술대회 논문집
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• pp.86-89
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• 1995

In this pacer, The effect of the impedances in SNOSEFT s memory devices has been developed. The effect of source and drain impedances are measuring using the method of the field effect bias resistance in the inner resistance regions of the device structure and external bias resistance. The effect of impedance by source and drain resistance shows according to increasing to the storage of memory charges, shows according to a function of decreasing to the gate voltages, shows the delay of threshold voltages, The delay time of low conductance state and high conductance state by the impedance effect shows 3 [${\mu}$sec] and 1[${\mu}$sec] respectively.

• 대한전기학회논문지:시스템및제어부문D
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• 제53권5호
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• pp.345-352
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• 2004

Currently, high data rate PLC(Power Line Communications), up to 100 Mbps, which use frequency bandwidth between 2 MHz and 30 MHz is investigated very hard, and commercial PLC modem for low voltage powerline network (indoor) is coming soon into communication market. For the purpose of developing a fit communication system which has little distortion of signal and attenuation, it is surely necessary to know about channel environments of powerline. Especially, the impedance measurement of the powerline and impedance matching are very important. As is known, since medium-voltage powerline (22.9 ㎸) is still working, it is not so simple to measure the powerline impedance. In our study, a portable impedance measurement equipment is developed. It consists of coupling capacitor, a drain coil and impedance matching transformer. The equipment is easily connected to medium voltage line and impedance of power line is measured using a network analyzer. Also, measurement results are used for impedance matching of PLC signal. In fact, matching transformer with several different impedances are used. The matching transformer is connected between coupling capacitor and signal port. In this paper, the developed portable impedance measurement equipment and impedance measurement results are presented. Also impedance matching technique using matching transformers will be explained. We showed the result of the improved performance by the impedance matching.

• 대한전기학회논문지:시스템및제어부문D
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• 제54권6호
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• pp.409-416
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• 2005

For broadband high-data-rate power line communication with the allocated frequency bandwidth from 2 to 30 MHz on medium voltage (MV) distribution power lines, a signal coupling unit is developed. The coupling unit is composed of a coupling capacitor for coupling communication signal, a drain coil, and an impedance matching part. The coupling capacitor made of ceramic capacitor is designed for transmission property of better than 1 dB in the frequency range. The drain coil is used for preventing low frequency high voltage from junction of medium voltage power line in case that a coupling capacitor is not working properly any more. Also, using ferrite core, a novel broadband impedance matching transformer is developed. A complete coupling unit with a coupling capacitor, a drain coil, and a matching transformer is housed by polymer for good isolation and distinguishing from high voltage electric facilities. Each is fabricated and its frequency behavior is tested. Finally, complete signal couplers are equipped in a MV PLC test bed and their performance are measured. The measurement shows that the coupling capacitor works excellently.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.60-63
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• 2003

This paper describes the design and the simulation of a V-band single pole double throw (SPDT) FET switch fur millimeter-wave applications using drain impedance transformation network with CPW transmission line. The designed switch has about 10% bandwidth at 60GHz. Insertion loss is better than 3dB fur the ON state and Isolation is larger than 30dB fer the OFF state. The maximum isolation is 43.4dB at 60GHz with input power of 10dBm. The yield analysis is done considering the effects of pHEMT variations.

• 한국전자파학회논문지
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• 제10권5호
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• pp.663-671
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• 1999

본 연구에서는 GaAs MESFET의 게이트-소오스 캐패시턴스($C_{gs}$)와 드레인-소오스 전류($I_{ds}$)의 비션형성에 의한 이득감소(Gain Compression) 및 위상왜곡(Phase Distortion)특성을 알아보고, 이를 최소화 할 수 있 는 소오스 및 부하 임피던스의 조건에 대해 조사하였다. 먼저 Volterra - Series 분석을 통하여, $C_{gs}(V_{gs})$와 $I_{ds}(V_{gs})$의 비선형특성을 조사하고, 각각의 비선형성분이 상호 소멸되는 소오스 및 부하 임피던스의 조건에서, 전체소자의 비선형성이 최소화 됨을 얄아보았다. 그리고 소오스 및 부하측정(Source, Load Pull)을 통하여 출 력전력값에 따라 최적의 선형성이 나오는 입출력 임피던스값을 찾고, Volterra-Series에서 구한 이론적인 결과와 비교 및 분석을 행하였다.

• 한국ITS학회 논문지
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• 제10권1호
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• pp.42-48
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• 2011

본 논문에서는 GaN HEMT (Gallium Nitride High Electron Mobility Transistor) bare-chip을 이용하여 X-대역에서 수동로드 풀(Passive load-pull)을 수행하였다. 열로 인한 특성 변화가 최소화 된 동작 조건을 얻기 위해 드레인 바이어스 전압과 입력 RF 신호를 펄스로 인가하였다. 전자기장 시뮬레이션과 회로 시뮬레이션을 병행하여, 와이어 본딩 효과를 고려하여 드레인 경계면에서의 정확한 임피던스 정합 회로를 구현하였다. 임피던스를 변화시키기 위해 마이크로스트립 라인 스터브의 길이가 조절 가능한 회로를 설계하였다. 펄스 로드 풀 실험 결과 8.5 GHz에서 9.2 GHz 대역에서 최대 42.46 dBm의 출력 전력을 얻었으며, 58.7%의 드레인 효율 특성을 얻었다.

• 전기전자학회논문지
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• 제2권1호
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• pp.15-23
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• 1998

본 논문에서는 DGFET를 이용한 초고주파용 분포형 믹서가 연구되었다. 분포형 믹서 회로는 게이트, 드레인 전송선로와 입, 출력단에서 정합회로 및 DGFET들로 구성된다. RF와 LO신호가 각 게이트 전송선로의 입력 단에 인가되면, DGFET의 전달 컨덕턴스를 통해 드레인 전송선로로 전달되며, 각 드레인단의 출력된 신호들은 설계에 따라 동위상으로 더해지게 되고, 이러한 형태의 믹서는 변환이득을 개선할 수 있을 뿐만 아니라 각 소자의 임피던스가 전송선로에 흡수되므로 초광대역을 특성을 갖는다. 또한, 보다 높은 주파수까지 광대역 특성을 갖게 하기 위해서 각 전송선로의 입 출력 단에 m-유도 영상 임피던스 개념을 도입하여 입 출력 단을 정합 하였다, 이러한 분포형 믹서를 마이크로스트립 기판 위에 설계 및 제작하였고 광대역 특성 및 변환이득, RF/LO 분리도 등을 컴퓨터 시뮬레이션 및 실험을 통해 검증하였다.

• 전자공학회논문지A
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• 제33A권6호
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• pp.52-61
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• 1996

In this paper, harmonic-tuning method to achieve the maximum efficiency is proposed. Harmonic tuning method is applied to the optimum load impedance of a class B amplifier, which is extracted by using the modified cripps method. High efficiency power amplifier utilizing GaAs MESFET is designed and fabricated in the 835MHz band. The performance of th eamplifier is presented by having output power of 30.8dBm, drain efficiency of 80.5% and power added efficiency of 66% with an associated power gain of 7.4dB.