• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제50권10호
• /
• pp.489-493
• /
• 2001

The on-current of offset and LDD structured devices in slightly decreased while the off-current are remarkably reduced and almost constant independent of gate and drain voltage because offset and LDD regions behave as a series resistance and reduce the lateral electric field in the drain depletion. Degradation of these devices is dependent upon the offset and LDD length rather than doping concentration in these regions. Also, degradation mechanism has been related to the interface generation rather than the hot carrier injection into gate oxide.

• 전산구조공학
• /
• 제2권4호
• /
• pp.79-88
• /
• 1989

철골 건축 구조물이 횡하중을 받을 때 합성보의 거동에 대한 연구가 수행되었다. 실험으로부터 얻어진 결과와 수치해석에 의한 결과를 이용하여 합성보의 강성과 연결부에서의 강도를 위한 수학적 모델이 연결부의 상세를 고려하여 개발되었다. 또한 캔티레버 합성보의 skeleton 곡선과 hysteresis 곡선을 위한 해석모델이 제시되었다. 탄성보와 부재내의 비탄성 변형이 응집된 양 단부스프링으로 구성된 단일요소모델에 의한 합성보 요소가 컴퓨터 프로그램, DRAIN-2D에 포함되었으며, 해석결과는 실험결과의 비교를 통해 검정되었다.

• 한국지반공학회:학술대회논문집
• /
• 한국지반공학회 2008년도 추계 학술발표회
• /
• pp.930-937
• /
• 2008

From the result of precise field investigation and stability analysis for the cut slope, following results were acquired. 1. The cause of the collapse of cut slope came from circle sliding collapse by fault zone which remained inner weathering zone. 2. The existing destructed soil and rock can be removed by reinforcement. And to prevent the additional destruction, it is judged that applying the method after relaxing the slope would be reasonable. 3. To make cut slope stable, soft rock layer should be done cutting 1:1.5 and 1:2.0 ~ 1:2.5 for weathered rock and soil layer. 4. Heavy water leakage section should be applied horizontal drain method so that water pressure should not act to the cut slope.

• 한국정보통신학회:학술대회논문집
• /
• 한국정보통신학회 2015년도 추계학술대회
• /
• pp.863-865
• /
• 2015

본 연구에서는 비대칭 이중게이트 MOSFET의 채널 내 도핑농도분포에 대한 드레인유도장벽감소(Drain Induced Barrier Lowering; DIBL)에 대하여 분석하고자한다. DIBL은 드레인 전압에 의하여 소스 측 전위장벽이 낮아지는 효과로서 중요한 단채널 효과이다. 이를 분석하기 위하여 포아송방정식을 이용하여 해석학적 전위분포를 구하였으며 전위분포에 영향을 미치는 채널도핑농도의 분포함수변화에 대하여 DIBL을 관찰하였다. 채널길이, 채널두께, 상하단 게이트 산화막 두께, 하단 게이트 전압 등을 파라미터로 하여 DIBL을 관찰하였다. 결과적으로 DIBL은 채널도핑농도분포함수의 변수인 이온주입범위 및 분포편차에 변화를 나타냈다. 특히 두 변수에 대한 DIBL의 변화는 최대채널도핑농도가 $10^{18}/cm^3$ 정도로 고도핑 되었을 경우 더욱 현저히 나타나고 있었다. 채널길이가 감소할수록 그리고 채널두께가 증가할수록 DIBL은 증가하였으며 하단 게이트 전압과 상하단 게이트 산화막 두께가 증가할수록 DIBL은 증가하였다.

• 한국가스학회지
• /
• 제12권3호
• /
• pp.64-67
• /
• 2008

초고압 공압용 패킹을 적용한 밸브를 개발하여 밸브의 수명 및 기밀도를 높이고자 하였다. 밸브핸들 부위를 통하여 잔압을 제거할 수 있는 구조를 구현하여, 별도의 드레인밸브가 필요 없는 효과적인 밸브를 개발하였으며 특성은 밸브 팩킹을 특수한 형태로 가공하고, 기둥에 드레인 홀을 구성하여, 밸브가 열리거나, 닫힌 상태에 관계없이 드레인이 가능하도록 하였다.

• Transactions on Electrical and Electronic Materials
• /
• 제12권6호
• /
• pp.245-248
• /
• 2011

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2009년도 제38회 동계학술대회 초록집
• /
• pp.140-140
• /
• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.

• 대한금속재료학회지
• /
• 제49권4호
• /
• pp.304-312
• /
• 2011

In this study, MOSFET type micro hydrogen gas sensors with platinum catalytic metal gates were designed, fabricated, and their electrical characteristics were analyzed. The devised MOSFET Hydrogen Sensors, called MHS-1 and -2, were designed with a platinum gate for hydrogen gas adsorption, and an additional sensing part for higher gas sensitivity and with a micro heater for operation temperature control. In the electrical characterization of the fabricated Pt-gate MOSFET (MHS-1), the saturated drain current was 3.07 mA at 3.0 V of gate voltage, which value in calculation was most similar to measurement data. The amount of threshold voltage shift and saturated drain current increase to variation of hydrogen gas concentration were calculated and the hydrogen gas sensing properties were anticipated and analyzed.

• Journal of information and communication convergence engineering
• /
• 제14권2호
• /
• pp.115-121
• /
• 2016

Currently there is a lack of literature on SPICE-level models of double-gate (DG) tunnel field-effect transistors (TFETs). A DG TFET compact model is presented in this work that is used to develop a SPICE model for DG TFETs implemented with Verilog-A language. The compact modeling approach presented in this work integrates several issues in previously published compact models including ambiguity about the use of tunneling parameters A_k and B_k, and the use of a universal equation for calculating the surface potential of DG TFETs in all regimes of operation to deliver a general SPICE modeling procedure for DG TFETs. The SPICE model of DG TFET captures the drain current-gate voltage (I_ds-V_gs) characteristics of DG TFET reasonably well and offers a definite computational advantage over TCAD. The general SPICE modeling procedure presented here could be used to develop SPICE models for any combination of structural parameters of DG TFETs.

• 한국정보디스플레이학회:학술대회논문집
• /
• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
• /
• pp.546-549
• /
• 2009

In this paper, we investigated the effects of different source/drain (S/D) electrode materials in thin film transistors (TFTs) based on indium-gallium-zinc oxide (IGZO) semiconductor. A transfer length and effective resistances between S/D electrodes and amorphous IGZO thin-film transistors were examined. Intrinsic TFT parameters were extracted by the transmission line method (TLM) using a series of TFTs with different channel lengths measured at a low drain voltage. The TFTs fabricated with Cu S/D electrodes showed the lowest contact resistance and transfer length indicating good ohmic characteristics, and good transfer characteristics with a field-effect mobility (${\mu}_{FE}$) of 10.0 $cm^2$/Vs.