• Journal of the Computational Structural Engineering Institute of Korea
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• v.13 no.2
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• pp.189-196
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• 2000

The objective of this paper is to propose an analysis technique to predict the behavior of PC wall structures subjected to cyclic load. While PC wall panel is idealized by finite elements, the joints at which PC walls are connected each other are idealized by nonlinear spring elements. Axial and shear spring elements are developed for simulating shear, compression and tension behaviors of joints. The strength and stiffness of each spring elements we presented from the previous research results and incorporated into the computer program of DRAIN-2DX. The proposed analysis technique is evaluated by analyzing specimens previously tested and comparing with those. On the strength, stiffness, energy dissipation and lateral drift, analytical results show good agreements with test results. This means the proposed technique is effective to predict the response of the PC wall structures.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.8 no.6
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• pp.558-567
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• 1997

Linear power amplifier modules with high-efficiency have been developed for PCS handy phone. These modules were designed using extracted large-signal models of MESFETs and harmonic balance simulation. The modules are intended for low-tier and high-tier at the operation frequency range of 1750 ~ 1780 MHz. For low-tier module, the output power and $IMD_3$ were 23.2 dBm and 31 dBc, respectively, at power-added efficiency of 34% with the supply drain bias of 3.6 V. For high-tier module, the output power and $IMD_3$ were 272.2 dBm and 31 dBc, respectively, at power-added efficiency of 33% with the supply drain bias of 4.2 V. These linear power amplifier modules are suitable for PCS handy phone.

• Journal of the Korean Geosynthetics Society
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• v.7 no.1
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• pp.39-44
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• 2008

Recently, the demand for industrial and residential lands are being increased with economic growth, however, it is difficult to acquire the land for development with good ground condition. For efficient and balanced development of land, new development projects are being carried out not only the areas with inland but those with the soft ground as well. As soft grounds have complex engineering properties and high variations such as ground settlement especially when their strength is low and depth is deep, it needs to accurately analyze the engineering properties of soft grounds and find general measurement for stabilization and economic design and management. Prefabricated vertical drain technology is widely used to accelerate the consolidation of soft clay deposits and dredged soil under the preloading and various types of vertical drain are being used with the discharge capacity. Under field conditions, the discharge capacity is changed with various reason, such as soil condition, confinement pressure, long-term clogging and folding of vertical drains, and so on. Therefore, many researcher and engineer recommend the use of required discharge capacity. In this paper, the experimental study were carried out for two different types of vertical drains by utilizing the large-scale model tests and waste lime.

• Journal of the Korean Geosynthetics Society
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• v.16 no.2
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• pp.165-174
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• 2017

There are natural disasters caused by abnormal climate in the world. In particular, there are frequent disasters such as floods and landslides caused by rainfall in summer. Rainfall will have a major impact on the stability of a retaining wall. If drainage during rainfall activities within the retaining wall is not made properly, permeated water brings a significant increase in pore pressure inside of the backfill soil and reduces the shear strength of the soil. Therefore, research how to install the drainage layers to reduce the infiltrated water inside of the backfill soil is very necessary. In this study, we performed a numerical modeling to find the optimum installation conditions of the location and number of drainage layer related to stability of the reinforced retaining wall during rainfall installed geosynthetics.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.255-255
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• 2010

Recently, nonvolatile memories (NVM) of various types have been researched to improve the electrical performance such as program/erase voltages, speed and retention times. Also, the charge trap memory is a strong candidate to realize the ultra dense 20-nm scale NVM. Furthermore, the high charge efficiency and the thermal stability of SiC nanocrystals NVM with single $SiO_2$ tunnel barrier have been reported. [1-2] In this study, the SiC charge trap NVM was fabricated and electrical properties were characterized. The 100-nm thick Poly-Si layer was deposited to confined source/drain region by using low-pressure chemical vapor deposition (LP-CVD). After etching and lithography process for fabricate the gate region, the $Si_3N_4/SiO_2/Si_3N_4$ (NON) and $SiO_2/Si_3N_4/SiO_2$ (ONO) barrier engineered tunnel layer were deposited by using LP-CVD. The equivalent oxide thickness of NON and ONO tunnel layer are 5.2 nm and 5.6 nm, respectively. By using ultra-high vacuum magnetron sputtering with base pressure 3x10-10 Torr, the 2-nm SiC and 20-nm $SiO_2$ were successively deposited on ONO and NON tunnel layers. Finally, after deposited 200-nm thick Al layer, the source, drain and gate areas were defined by using reactive-ion etching and photolithography. The lengths of squire gate are $2\;{\mu}m$, $5\;{\mu}m$ and $10\;{\mu}m$. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer, E4980A LCR capacitor meter and an Agilent 81104A pulse pattern generator system. The electrical characteristics such as the memory effect, program/erase speeds, operation voltages, and retention time of SiC charge trap memory device with barrier engineered tunnel layer will be discussed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.4
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• pp.760-765
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• 2007

In this paper, the threshold voltage roll-off and drain induced barrier lowering(DIBL) have been analyzed for nano structure double gate FinFET. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics were used to calculate thermionic omission current, and WKB(Wentzel- Kramers-Brillouin) approximation to tunneling current. The threshold voltage roll-offs are obtained by simple adding two currents since two current is independent. The threshold voltage roll-off by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the threshold voltage roll-off and DIBL are very large. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects, and this process has to be developed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1615-1622
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• 2008

We have fabricated the poly-silicon thin film transistor(TFT) which has the LDD-region with graded spacer. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $H_2$/plasma processes were fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring/analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplicities of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of Adhesion and Interface
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• v.21 no.4
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• pp.129-134
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• 2020

Understanding charge trapping at the interface between conjugated semiconductor and polymer dielectric basically gives insight into the development of long-term stable organic field-effect transistors (OFET). Here, the charge transport properties of OFETs using polymer dielectric with various molecular weights (MWs) have been investigated. The conjugated semiconductor, pentacene exhibited morphology and crystallinity, insensitive to MWs of polymethyl methacrylate (PMMA) dielectric. Consequently, transfer curves and field-effect mobilities of as-prepared devices are independent of MWs. Under bias stress in humid environment, however, the drain current decay as well as transfer curve shift are found to increase as the MW of PMMA decreases (MW effect). The charge trapping induced by MW effect is irreversible, that is, the localized charges are difficult to be delocalized. The MW effect is caused by the variation in the density of polymer chain ends in the PMMA: the free volumes at the PMMA chain ends act as charge trap sites, corresponding to drain current decay depending on MWs of PMMA.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.68-71
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• 2004

Recently, a great deal of research and development of a fuel cell have been carried out to solve problems on the drain of fossil fuel, air pollution and global warning. In order to improve the efficiency of a fuel cell, it is necessary to clarify the flow in separator. In this study, distributions of velocity flow rate and pressure, and streamlines are examined in detail from numerical analysis with CFD code. In the experiment the distribution of flow rate is measured and flow in the each grooves of the separator is visualized by dye method changing Reynolds number. Furthermore, effects of size of the inlet and outlet manifolds and shape of ribs near the inlet outlet on the distributions of flow and pressure are examined.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.455-459
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• 2004

Electrostatic discharge(ESD) is a serious reliability concern. It causes approximately most of all field failures of integrated circuits. Inevitably, future IC technologies will shrink the dimensions of interconnects, gate oxides, and junction depths, causing ICs to be increasingly susceptible to ESD-induced damage [1][2][3]. This thesis shows the optimization of the ESD protection circuit based on the tested results of MM (Machine Model) and HBM (Human Body Model), regardless of existing Reference in fully silicided 0.18 um CMOS process. His thesis found that, by the formation of silicide in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness [8].